Design Article
Discrete audio amplifier basics - Part 2: JFETs, MOSFETs and other circuit configurations
John Linsley Hood
3/24/2010 2:40 PM EDT
Although JFETs will work in most of the circuit layouts shown for junction transistors, the most significant difference in the circuit structure is due to their different biasing needs. In the case of a depletion mode device it is possible to use a simple source bias arrangement, similar to the cathode bias used with an indirectly heated valve, of the kind shown in Figure 9.13.
Figure 9.13: Simple JFET biasing system.
As before, the source resistor, R3, will need to be bypassed with a capacitor, C2, if the loss of stage gain due to local NFB is to be avoided. As with a pentode valve, which the junction FET greatly resembles in its operational characteristics, the simplest way of calculating stage gain is by the relationship:
The device manufacturers will frequently modify the structure of the JFET to linearize its Vg/Id characteristics, but, in an ideal device, these will have a square-law relationship, as defined by
For a typical JFET operating at 2 mA drain current, the gfs value will be of the order of 1"4 mS, which would give a stage gain of up to 40 if R2, in Figure 9.13, is 10 kΩ. This is very much lower than would be given by a BJT and is the main reason why they are not often used as voltage-amplifying devices in audio systems unless their very high input impedance (typical values are of the order of 1012 Ω) or their high, and largely constant, drain impedance characteristics are advantageous.
The real value of the JFET emerges in its use with other devices, such as the bipolar/FET cascode shown in Figure 9.14 or the FET/FET cascode layout of Figure 9.15.
Figure 9.14: Bipolar/FET cascode.
Figure 9.15: FET/FET cascode.
In the first of these, use of the JFET in the cascode connection confers the very high output impedance of the JFET and the high degree of output/input isolation characteristic of the cascode layout, coupled with the high stage gain of the BJT. The source potential of the JFET (Q2) will be determined by the reverse bias appearing across the source/gate junction, and could typically be of the order of 2"5 V, which will define the collector potential applied to Q1.
A further common application of this type of layout is that in which the cascode FET (Q2 in Figure 9.15) is replaced by a high-voltage BJT. The purpose of this arrangement is to allow a JFET amplifier stage to operate at a much higher rail voltage than would be allowable to the FET on its own; this layout is often found as the input stage of high-quality audio amps. A feature that is very characteristic of the JFET is that for drain potentials above about 3 V, the drain current for a given gate voltage is almost independent of the drain voltage, as shown in Figure 9.16.
Figure 9.16: Drain current characteristics of junction FET.
BJTs have a high characteristic collector impedance, but their Ic/Vc curve for a fixed base voltage, also shown, for comparison, in Figure 9.16, is not as flat as that of the JFET. The very high dynamic impedance of the JFET resulting from this very flat Id/Vd relationship encourages the use of these devices as constant current sources, shown in Figure 9.17.
Figure 9.17: Current source layout.
In this form the JFET can be treated as a true two-terminal device, from which the output current can be adjusted, with a suitable JFET, over the range of several milliamperes down to a few microamperes by means of RV1.
Next: MOSFETs
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wreeve
3/28/2010 12:39 AM EDT
I would like to explore the cascode configuration of fig. 9.15 but with Q2 replaced with a BJT. My question concerns biasing of Q2 when it is a BJT in a common base configuration. Does it matter if the base biasing resistor is connected directly to Vcc or the bottom of R2 where the Output is tapped? How do both arrangements affect the overall cascode circuit gain?
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bcarso
3/28/2010 4:09 PM EDT
You need to establish a base bias suffficent to operate the lower device in/near the pinchoff region, i.e., where its output impedance is reasonably high. You do not want the base voltage to (partially) track with the circuit output voltage---this tends to defeat the purpose of the cascade, which is to minimize the voltage swing on the drain of the input device, thus reducing drain-gate capacitance multiplication ("Miller effect"). In some cases it is advantageous to derive the base voltage from a sample of the actual circuit input voltage, reducing the effective FET input capacitance further---however, this will result in negative input impedance at high frequencies and potential instabilities.
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WKetel
3/31/2010 8:18 PM EDT
This explanation of the symbols is useful. Now I need to convince others that it has value.
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kendallcp
7/20/2010 8:34 AM EDT
It's lovely to see such extended treatment of JFET amplifiers. How many other people out there get the same rather wistful feeling that I do, though? The big semiconductor manufacturers have culled their JFET ranges to extinction, leaving the market mostly to specialist vendors such as Linear Systems. Depletion-mode FETs have the wonderful characteristic of being conducting when no gate potential is applied; this behaviour is really hard to replicate otherhow. There are a few depletion MOS devices out there; single-source and in quite large packages. I feel rather sad that the JFET is slowly fading from our design consciousness. What do you think?
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