Design Article

IMG1

Infrastructure DSPs for the triple-play era

Leon Adams, Texas Instruments

9/27/2007 3:00 AM EDT

[For related news, see TI unveils fastest-ever DSP.]

As multimedia content grows along with total traffic, equipment manufacturers are faced with unprecedented engineering challenges and opportunities. They must build a new generation of equipment that can handle a sharp and continuous rise in aggregate traffic that is is fundamentally different than the voice and data traffic that drove infrastructure design paradigms of the past.

Since the computer revolution of the 1970s, several trends have combined to drive this change:

  • The shift from voice only to voice and data traffic. This trend began decades ago and is well underway.

  • The addition of multimedia traffic— particularly streaming media— to the existing voice and data traffic. This trend is evidenced by telcom carriers shifting to "triple play" services offering voice, video, and data service.

  • The evolution from fixed-location services to home services to mobile services. The same voice-to-data-to-media evolution of the wired infrastructure is now underway in wireless.

  • These first three trends have driven another – the move from circuit switched transport to packet-based transport, specifically to Internet Protocol (IP) traffic.

In the days of voice, telecom signal processing was limited to not much more than echo cancellation, line conditioning for data modems, and signal processing for modulating and demodulating data over the switched circuits. Today, dozens of signal processing algorithms are used to digitally encode/decode and compress/decompress audio, video and data traffic. In short, telecom infrastructure is not only handling more data but also experiencing an exponential jump in the amount of signal processing that must be applied to that data.

Obviously, a large boost in performance is needed to meet this exponential jump. One way to do this would be to simply crank up the clock speed of the digital signal processor (DSP). This solution falls short for a number of reasons. For one, there are limits on how fast a chip can clock. For another, with the traffic load increasing not linearly but exponentially, performance requirements will soon outpace even the highest clock rate. Another fundamental problem is that infrastructure equipment is rack-mounted with stringent size and heat dissipation limitations. With the size of the rack not changing, except to get smaller, the high heat dissipation caused by high clock speeds will eventually make cranking the clock speed higher unfeasible. In the future, the ability to deliver more performance to the board will be limited by the power dissipation budget for the board, the age and location of the buildings, and racks that house infrastructure equipment.

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