Integrating audio codecs in next-generation SoCs for smartphones and tablets

Introduction
Integrating audio IP that has been silicon proven and optimized for specific audio functions helps reduce power, area, and cost in today's multimedia system-on-chips (SoCs). As next-generation designs migrate to 28-nanometer (nm) process technologies however, new integration challenges arise. Audio functionality that exists in audio codecs consists mainly of analog circuitry, which does not scale with process technology, and therefore does not follow the traditional Moore's Law.

System architects and SoC designers need to take into consideration how the increased wafer pricing of 28-nm process technologies impacts the economics of incorporating audio codecs into advanced SoCs. Synopsys has performed testing on several mobile multimedia devices available in the market today, finding that most current models of smartphones and tablets can be supported with audio codecs developed in 28-nm.

This article presents the test results and discusses the business and technical challenges of integrating audio functionality into a 28-nm mobile multimedia SoC, while also offering insight on how to overcome those challenges. Some key design considerations are also explained, including scaling limitations, supply voltage requirements and system partitioning options.

Audio Codec Basics
For clarity and the purpose of this discussion, an audio codec can be described using Figure 1 below. An audio codec contains microphone and line inputs, signal routing and mixing, amplifier blocks, and multiple ADC and DAC channels. It also consists of a variety of output drivers, including line outputs, headphone, and loudspeaker drivers as well as a small digital processing block consisting of decimating/interpolating filters and a standard I2S digital audio interface.

Cost Considerations at 28-nm Process Technologies
At 28-nm process technologies, the wafer costs are expected to be significantly higher than in 65-nm technologies. For digital circuits that follow Moore's Law, the higher wafer cost can be compensated through an increase in gate density, the possibility of more functionality being incorporated into the same area and higher performance.

Analog circuits such as audio codecs make extensive use of the I/O devices and therefore do not scale with process nodes in the same way that digital circuits that use primarily core devices do. Higher wafer costs will create a significant increase in the overall silicon cost of audio technology, unless the area can be reduced by 25-30%.

For example, an audio codec implemented in 2.5 mm² in a 65-nm technology would need to decrease to 1.9 mm² in a 28-nm process in order to keep the silicon cost the same. Figure 2 below shows the forecasted cost per 12" wafer in 2013, normalized to a 65-nm process. The cost of a 28-nm wafer in production is expected to be almost 40% higher than a 65-nm wafer.

Because there is not a significant performance improvement in audio circuits in 28-nm technologies, when compared to the same functions in 65-nm technologies, one of the critical factors in determining whether to integrate audio functionality is the silicon cost. Figure 3 shows the area required across different process technologies to achieve the same silicon cost as a 2.5 mm² audio codec in 65-nm.

The following sections discuss the key technical challenges of integrating audio codecs in 28-nm process geometries. Each of these challenges can be addressed with circuit or system modifications to deliver the most optimal power and cost for the SoC.