Integrating audio codecs in next-generation SoCs for smartphones and tablets

There are three main circuit blocks that limit how much an audio codec scales with process technologies:

• Active amplifiers and resistor ladders: Active amplifiers and resistive ladders are used in a multitude of volume controls and switches that mix different audio sources together. Active amplifier performance is limited by device matching characteristics. Reducing the area of the individual devices negatively impacts the device matching and significantly degrades the active amplifier performance. For this reason, active amplifiers in 28-nm process nodes are not significantly smaller in area than amplifiers with the same performance in 40-nm or 65-nm processes. In order to avoid any noticeable artifacts such as zip noise, the volume gain steps need to be below 1 dB. This requires the resistive ladder to have a large number of taps, which increases the overall area.
• Data converters: Most audio codecs are implemented with sigma-delta ADC and DAC circuits. The noise level in the switched capacitor circuits is inversely proportional to the capacitance. This puts a minimum capacitance value required for a given audio performance requirement, therefore, the capacitor area will not scale with process node. Further complicating matters, as the supply voltage reduces from 2.5 V (or 3.3 V) down to 1.8 V in 28-nm processes, in order to maintain the same dynamic range, the noise level must be reduced. The capacitors must increase in both area and capacitance.
• Output drivers: Large output currents must be delivered with low distortion. In order to support the large output currents needed to drive the headphones and loudspeakers, the output devices must be very large and will not scale with process technology. Similar to the data converter block, and as discussed in more detail below, the output driver circuit area and performance is impacted by the migration from 2.5 V to 1.8 V supplies.

The following two sections investigate the trade-offs and impact of implementing output drivers in a 28-nm process with a 1.8 V supply.