Slew rate in the two-stage topology
The last difficulty of the two-stage topology shown in figure 1 which I'll discuss here is related to slew rate. While the output of the second stage can sink very high currents by turning on Q6, current sourcing is limited by I2. This can lead to a slew rate limitation, particularly as under transient conditions the output current of I2 may be reduced by junction capacitances , and if the output stage demands high drive currents.
I have presented a solution to this in , but there are some limits to its effectiveness. Of course it is very arguable whether there are any audible artefacts from such slew rate limitations within a well designed amplifier . Nonetheless, at least from a marketing point of view, it is desirable to tackle this issue.
To make the sourcing and sinking output current capabilities of the second stage equal, and as a first-order approximation unlimited, many prior art amplifiers have implemented a push-pull arrangement similar to that shown in figure 2. To derive the complementary drive signals required for the transimpedance stage formed by Q9–Q12, two complementary differential pairs (Q1–Q4) are employed. Not shown in the schematic diagram is the bias current control necessary for the second stage; some solutions for this are presented in [2,5,7,8].
Figure 2: Basic two-stage amplifier with push-pull transimpedance stage. Necessary bias control circuit for the second stage is omitted.
While this amplifier topology, with some minor modifications of the input stage, easily supports very high slew rates (see e.g., ), it does not fully solve the power supply rejection issue discussed above. Due to the complementary nature of the topology both power supply rails now act as main injection route. However, as is easily shown by simulation or other forms of sufficiently detailed theoretical analysis, the injection from the negative power supply rail is reduced by 6 dB compared to the amplifier from figure 1 for a given amount of loop gain.
Furthermore ripple signals which are present in a complementary form on both power supply rails are theoretically rejected. But this rejection mechanism is not particularly reliable, as it depends, e.g., on the matching of the smoothing capacitors employed in the positive and negative power supply rail. So this amplifier architecture has again to rely on either RC filtering, additional power supplies for the small-signal stages or Ahuja compensation for excellent power supply rejection.
Further minor problems with this topology arise from gain mismatch in the two complementary halves.3 This can lead - according to simulation results - to both additional distortion and instability, although at least the latter is easily fixed by connecting a small capacitor across the inputs of the second stage (i.e. the bases of Q9 and Q10).
Excellent power supply rejection can be achieved by the use of a differential transimpedance stage as shown in figure 3. The second stage is formed by Q5–Q8, and its output is converted to single ended by the current mirror realised by Q9 and Q10; biasing is provided by I2.
Figure 3: Amplifier topology with differential transimpedance stage.
Besides the Miller compensation capacitor C2 there is now an additional capacitor (C1) which has an (although only second order) influence on compensation. It is required to make the drive from the input stage single-ended at high frequencies, as otherwise the output current of Q2 would bypass the Miller compensation loop at high frequencies.
The conversion of the differential output current of the input stage to a single- ended output voltage is, thanks to the ground connection of C1, carried out with respect to ground. Ripple of the negative power supply is present at the base of both Q5 and Q6; however this appears as a common-mode signal to the transimpedance stage and hence is rejected because of the differential nature of this stage. The rejection is mainly limited by mismatch of C1 and C2; for best results these should hence be 1% parts.
It cannot be stressed enough that C1 needs to be grounded for good power supply rejection. Most amplifiers that use a similar topology (and that I've evaluated), connect this capacitor to the collector of Q7; presumably in an attempt to make it a Miller compensation capacitor as well, but this cannot happen as there is no significant voltage swing at this node. However this arrangement will effectively connect C1 to the positive power supply rail through the current mirror input, putting power supply rejection back to the point of the simple two-stage amplifier of figure 1.
Also detrimental to the performance of this topology is the use of a standard current mirror instead of the active load formed by Q3 and Q4. The main disadvantage of this topology relates to the voltage headroom required by I2; it directly reduces available output voltage swing which is highly undesirable. Also both sourcing and sinking output current capability of the second stage is limited by I2; hence the support of very high slew rates will again be difficult at some point, particularly if the output stage demands substantial drive current.
As we have seen from this discussion of two-stage topologies there is no known architecture which simultaneously achieves inherently excellent power supply rejection and freedom from second-stage slew rate limits. In the following section I will present a novel amplifier topology which does just this.
3 The gain of one complementary half is defined as the transconductance of that differential pair times the corresponding Miller compensation capacitor. Gain mismatch can hence arise both from the input stage transconductances or the compensation capacitors.