Design Article
Audio amplifier topology with push-pull transimpedance stage - Part 3: Experimental verification
Samuel Groner
10/24/2012 11:28 AM EDT
This article originally appeared in Linear Audio Volume 2, September 2011. Linear Audio, a book-size printed tech audio resource, is published half-yearly by Jan Didden.
[Part 1 introduces an audio amplifier topology which uses a novel push-pull transimpedance stage that offers a substantial improvement in power supply rejection over standard amplifier configurations. Part 2 discusses the amplifier's biasing, stability and AC performance.]
9. Experimental VerificationTo compare the audio performance of the new transimpedance stage to the standard amplifier topology from figure 1, a model amplifier (that is, an amplifier with a small-signal output buffer only, which is powered from low voltage regulated supplies [1]) for each topology was built. Figure 11 depicts the implementation which was chosen for the standard topology, and in figure 12 the model amplifier for the novel transimpedance is shown.
To make the results as fair as possible, the input differential pairs have the same quiescent current and emitter degeneration, and the compensation capacitors have alike values. Furthermore, the quiescent current of the emitter followers and the common emitter transistors in the transimpedance stage, as well as the emitter resistor values of the common- emitter transistors, are made equal. Obviously, also the small-signal class A output stage details are equivalent. For simplicity, the use of voltage regulators for the front-end of the new amplifier was omitted.
If measured at a noise gain of 22 (which gives a unity loop gain frequency of about 700 kHz), +20 dBu output level and within a 80 kHz bandwidth, THD+N of both amplifiers is below –112 dB across the full audio frequency range, and dominated by amplifier noise and residual contributions of the oscillator and analyzer. This indicates that both topologies have no inherent distortion mechanisms in the small-signal stages which were significant in the context of a full power amplifier design. Substantial differences however are observed if the two amplifiers are evaluated for their sensitivity to loading at the second stage output node.
In [5] I have introduced the use of a voltage-dependent network, consisting of two back-to-back connected 3.3 V zener diodes in series with a 10 kΩ resistor, to roughly model the loading behaviour of power output stages. There is no reason to suspect that this modeling is particularly accurate, however it enables the easy comparison of amplifier topologies regarding the sensitivity to this distortion mechanism,which is just what we need here. Figure 13 discloses the measurement results; without doubt they provide little evidence for arguing against the novel transimpedance stage.
At low frequencies, the standard amplifier topology shows a mixed distortion residual, while the new amplifier architecture is still limited by noise and oscillator/analyzer contributions. Above 1 kHz, both model amplifiers show increasing distortion levels, however the magnitude observed for the novel transimpedance stage remains about dB below that of the conventional arrangement. Note that the decrease in distortion above 2 kHz is due to the bandwidth limiting filter and not actual circuit behaviour.
Unfortunately detailed discussion of the reasons which lead to the superiority of the new second stage with regard to output loading are beyond the scope of this article. I can just refer to the analysis I presented in [5], and give some food for thought in the following listing:
- The lumped resistance at the input node of the second stage is considerably higher for the new topology; this is because of the use of folded cascodes (which have higher output resistance than a differential pair), the current mirror with high emitter resistor values (which increases its output resistance), and the high-value resistors which are used to bias the emitter followers (R9 and R10 in figure 12). The high lumped resistance leads to low second stage output impedance.
- The complementary push-pull arrangement further reduces second stage output impedance, and mitigates the dependence of output impedance on output current.
- The novel transimpedance stage shows reduced nonlinear modulation of the compensation capacitor reference voltage (i.e. the second stage input node voltage). This is because the complementary topology cancels even-order harmonics present at the transimpedance stage input node.
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pcsalex
10/25/2012 7:18 AM EDT
Figure 12, Q9 and Q10 collectors shorted!
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pcsalex
10/25/2012 7:21 AM EDT
sorrry figure 12 Q9 and Q10 base are shorted ?
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ZekeR
11/2/2012 5:04 PM EDT
It's okay. Q9 and Q10 minimize the stage's crossover distortion. Their bases are meant to be connected.
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Fabio007
11/5/2012 2:48 AM EST
Q9, Q10 with collectors together and to gnd, and bases together: Yes I can see that these just buffer the signal (current) at Q5 collector before reaching Q11 Q12, however I would feel more comfortable it they operated with some voltage across their respective CB junctions - at least the SPICE modelling would be more accurate, I think; plus the Ft should be better (higher), so maybe those feed-forward capacitors C4, C5 could be smaller. A Vbe multiplier (or diode string) between collectors of Q5 and Q8 (with bypass capacitor) would be just fine for this, so that Q9 and Q10 both operate with Vcb of about 2V. This would not affect Q11 and Q12 except for reselecting bias resistors R13, R14.
Also I note there is just one diode string for the bias voltages for the output stage and input stages. This means signal (and load) current modulation of the base currents of Q15, Q16 will affect currents flowing in bias diodes D1 to D10, which will then affect the other stages.
Question: is there a reason the bias voltage for input stage (Q3, and Q4, Q5) is higher that of the output stage Q15, Q16 (5 diode drops vs just 2), or is this an attempt to reduce the aforementioned bias voltage modulation without resorting to separate bias networks and their associated increased bias current?
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Fabio007
11/7/2012 5:53 AM EST
This is a good topology; it has nice features (like the signal remaining a current right up until being converted to a voltage by a well-biased common-base stage that can charge/discharge capacitances rapidly). However, I’m not so sure the comparison of the “amplifier with new trans-impedance stage” in fig 12 with the “standard 2 stage topology” of figure 11 is entirely fair.
The amplifier of fig 12 has an extra transistor providing gain compared to the amplifier of fig 11. In Fig 12 the current signal output of the differential stage (the folded cascade stage does not amplify, it only provides a level-shifting function) is amplified by TWO transistors: both Q9 and Q11. This amplified current then gets converted to a voltage by the common-base amplifier stage Q15. This is three (3) transistors in total providing the gain of the output signal from the differential stage. Compare this with figure 11. Only Q6 and Q7 (forming a trans-impedance amplifier) amplify the output of the differential stage.
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Fabio007
11/7/2012 5:53 AM EST
Further, in Fig 11 the output stage is not complementary (push-pull) driven as is the case in Fig 12. In fig 11 Q7’s collector is loaded by a standard constant current source formed by Q9. In fig 12, Q10, Q12, form the complementary driver for Q16; there is no such complementary driver for Q9 in Fig 11.
Note also the extra bias current of fig 12, where Q9 is biased at 1mA, Q11 at 6mA, and Q15 at 7mA. Whereas in fig 11 the trans-impedance stage has bias currents of 1mA for Q6, and 6mA for Q7; there is no third stage biased at a current close to that of Q7.
Looking at transistor count: Fig 11 has a total of 11 transistors. Fig 12 has a total of 18; the extra 7 transistors are due to:-
a) folded cascade level shifter (3 extra if we include Q6);
b) one extra gain transistor (Fig 12s Q11)
c) three extra for the complementary driver (Fig 12s Q10, Q12, Q14).
For a fair comparison pitting purely topology against topology, perhaps it would be fairer to throw an extra 7 transistors at Fig 11 (say, by adding an extra gain transistor between Q6 and Q7 biased at about 6mA, and then add a complementary driven load for collector of Q7), and then seeing how they compare.
If that is done, then it may well happen that the amplifier of Fig 12 may still come out ahead for the measurements of interest (THD +N, and power supply ripple rejection); but I suspect the difference may not be all that great.
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