Audio amplifier topology with push-pull transimpedance stage - Part 3: Experimental verification

Next I have evaluated the equivalent input noise of both amplifiers. Measured in a 22 Hz to 22 kHz bandwidth, the amplifier from figure 11 achieves –122.6 dBu (this includes the noise from the feedback network, with an effective total resistance of 98Ω). While this is already an excellent figure, the new amplifier topology does even better with –124.5 dBu.

Despite the additional noise contribution of the folded cascodes, this leads to overall better noise performance for the novel amplifier architecture. The emitter resistors of the standard topology cannot be made significantly larger without further circuit changes, as the current mirror output might become saturated under certain conditions.

Well-mannered overload behaviour is, particularly with more complex amplifier topologies, not always easily achieved. Typical artefacts include [2]:

• Polarity reversal during clipping
• Oscillation during, or during recovery from, clipping
• Prolonged recovery from clipping

Fortunately the basic overload behaviour of the novel amplifier topology is quite good; figure 14 depicts the output voltage of the model amplifier from figure 12 attempting to provide a 10 kHz, 4 V_PP triangle waveform output with ±15 V power supplies. There is some prolonged recovery from clipping discernible, but no polarity reversal or instability.

In contrast, the standard amplifier topology shows distinctly asymmetric overload behaviour, and for negative clipping, considerable artefacts (see figure 15). While I do not believe that there are drastic audible differences between the overload behaviour of the two amplifier topologies - last but not least, serious clipping sounds pretty bad anyway, and the observed artefacts occur in the µs range - an oscilloscope display similar to figure 14 will surely please a reviewer's eyes much more than one close to figure 15.

These measurements neglect the contribution of the power transistors in the output buffer. Often these suffer themselves from considerable recovery time [2], and it may be desirable to prevent saturation of these transistors by clamping the output voltage of the transimpedance stage to a well defined threshold below the power supply voltage. Implementation of such a clamping arrangement is often difficult, particularly because it must not impair the distortion performance of the amplifier below clipping. Some possible implementations may be found in [2].

As the model amplifier from figure 12 does not implement voltage regulators for the amplifier front end, and hence the potential power supply rejection advantage of the new topology is not fully realised, I have not carried out detailed power supply rejection measurements yet. Initial measurements however indicate that the main injection mechanism is indeed absent, and that the model amplifier from figure 12 has - even without the voltage regulators - overall better power supply rejection than the standard amplifier implementation shown in figure 11.

Last but not least the slew rate of these two model amplifiers was evaluated. The measurement results were +46.8 V/µs and –45.6 V/µs for the standard topology and +42.3 V/µs and –43.4 V/µs for the novel amplifier. These results are mainly determined by the primary slew rate limitation (finite output current of the input stage), which masked the expected advantage of the novel topology. The overall lower slew rate of the novel amplifier is probably just a result of parts tolerances, which lead to lower input stage quiescent current; possibly there is also a minor systematic effect from the input stage folded cascodes.

To also model the, at high frequencies potentially considerable, drive current demand of a power output stage, I've added a 3.3 kΩ resistor from the second stage output node to ground. This was sufficient tomake the slew rate behaviour of the standard topology more asymmetric (the measured values are +42.4 V/µs and –44.6 V/µs). The new push-pull configuration however easily supported the increased output current. The resulting slew rates are +41.4 V/µs and –42.6 V/µs, which is nearly the same as what is observed without the loading resistor.

To more thoroughly verify the absence of slew rate limitations in the second stage, I have also constructed a model amplifier based on the topology sketched in figure 8, using the input stage modifications derived in [8] and the very same second stage implementation as shown in figure 12. With a total input stage quiescent current of about 20 mA, and a compensation capacitor of 100 pF, the achieved slew rate was +226.6 V/µs and –228.3 V/µs. Additional loading at the transimpedance stage output altered this to just +223.5 V/µs and –222.4 V/µs.

This is enough evidence to conclude that the novel transimpedance stage indeed supports very high slew rates; simulation results indicate that, with appropriate changes to the input stage, much higher values are theoretically possible. However the effects from finite small-signal bandwidth soon makes further efforts in this direction meaningless.