Design Article
Audio amplifier topology with push-pull transimpedance stage - Part 3: Experimental verification
Samuel Groner
10/24/2012 11:28 AM EDT
Conclusion
10. Conclusion
In this article I have presented a new transimpedance topology, suitable for combination with a wide range of input stages to form amplifiers with two gain stages. Compared to prior amplifier designs, the novel architecture shows distinct advantages. First of all, it features inherently good power supply rejection, which is easily improved further by the use of voltage regulators for the amplifier front end. These voltage regulators are easily implemented at low cost and complexity. The transient current output capability of the new transimpedance stage is considerably enhanced as well, and will easily support the design of amplifiers with very high slew rate. This comes along with reduced sensitivity to loading at the second stage output node - this is a very welcome property, as it simplifies the design of the power output stage. Also the clipping behaviour was shown to be superior to the standard amplifier topology. The novel second stage topology requires level shifting at the input stage via folded cascodes. I have outlined how their impact on offset and voltage noise can be minimised, and shown that the noise performance of an amplifier using the new transimpedance stage may even be superior to prior implementations; that is because of reduced current mirror noise contribution. There is a complexity penalty associated with the new circuits, compared to the standard amplifier implementation. However, there is no significant cost increase to be expected, as just small-signal transistors and standard passive components are needed. Also the increased quiescent current is usually of no relevance within the context of a full power amplifier design. I must leave the design of a fully worked out power amplifier design, using the new concepts presented here, to future research. However, the interested reader will find it easy to derive his own implementation from the presented model amplifier. If, as suggested in section 7, voltage regulators for the amplifier front-end are used, the design from figure 12 will only need minor modifications in the folded cascodes of the transimpedance stage to accept high voltage power supply rails. With the addition of a suitable power output buffer, and the necessary control and protection circuitry, a complete power amplifier is realised. To the best of my knowledge this new amplifier topology is first officially published in this article. However it is not possible to investigate all prior art, particularly all the information buried within the extensive patent repository. I shall be happy to hear about any findings with this respect from my valued readers. In Part 4: Appendix: Noise in folded cascode stages. 11. Acknowledgements
I'm very grateful to Bob Cordell for reviewing this text and for providing valuable thoughts on it. I'd like to express my thanks to Jan Didden for his efforts in publishing this article and for providing us with an excellent resource on audio electronics. References
[1] Douglas Self: Audio Power Amplifier Design Handbook, 5th edition, Focal Press, 2009
[2] Bob Cordell: Designing Audio Power Amplifiers, 1st edition, McGraw-Hill, 2010
[3] J. E. Solomon: The Monolithic Op Amp: A Tutorial Study, IEEE J. Solid-State Circuits, vol. 9, no. 6, pp. 314–332, December 1974
[4] Bhupendra K. Ahuja: An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 629–633, December 1983
[5] Samuel Groner: Comments on Audio Power Amplifier Design Handbook by Douglas Self, February 2011, available for download from www.sg-acoustics.ch/analogue_audio/power_amplifiers/pdf/audio_power_amp_design_comments.pdf
[6] Bruno Putzeys: The F-word - or, why there is no such thing as too much feedback, Linear Audio, vol. 1, pp. 112–132, April 2011
[7] Royal A. Gosser, Jeffrey A. Townsend: Integrated-Circuit (IC) Amplifier With Plural Complementary Stages, US Patent 5,537,079, filed December 1994, issued July 1996
[8] Giovanni Stochino: Ultra-fast amplifier, Electronics &Wireless World, pp. 835–841, October 1995
[9] Alberto Bilotti: Noise Characteristics of Current Mirror Sinks/Sources, IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp. 516–524, December 1975
[10] William H. Gross: New High Speed Amplifier Designs, Design Techniques and Layout Problems, Analog Circuit Design: Operational Amplifiers, Analog to Digital Convertors, Analog Computer Aided Design, Springer, 1993
[11] William F. Davis, Robert L. Vyne: Design Techniques for Improving the HF Response of a Monolithic JFET Operational Amplifier, IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 978–985, December 1984
[12] Graeme John Cohen: Double Balanced Microphone Amplifier, AES preprint, no. 2106, August 1984
[13] Bruno Putzeys: High-Performance Discrete Building Blocks for Balanced Audio Signal Processing, AES preprint, no. 6294, October 2004 About the author
Samuel Groner was born and currently lives in Zurich, Switzerland. He has been passionate about both art and science as long as he can remember. At present he works for Weiss Engineering Ltd. in the field of analogue hardware design and freelances as classical recording engineer/producer. Besides this, he teaches several courses at a local sound engineering school (ear training, classical music production and audio measurement) and enjoys a manifold activity as pianist, singer and choirmaster. If time permits, he is found on one of the numerous Swiss hiking trails, preferably in company with one of his cameras and a few sheets of black-and-white film. He holds a MSc degree in computer science and a MA degree as Tonmeister (recording engineer/producer).
10. Conclusion
In this article I have presented a new transimpedance topology, suitable for combination with a wide range of input stages to form amplifiers with two gain stages. Compared to prior amplifier designs, the novel architecture shows distinct advantages. First of all, it features inherently good power supply rejection, which is easily improved further by the use of voltage regulators for the amplifier front end. These voltage regulators are easily implemented at low cost and complexity. The transient current output capability of the new transimpedance stage is considerably enhanced as well, and will easily support the design of amplifiers with very high slew rate. This comes along with reduced sensitivity to loading at the second stage output node - this is a very welcome property, as it simplifies the design of the power output stage. Also the clipping behaviour was shown to be superior to the standard amplifier topology. The novel second stage topology requires level shifting at the input stage via folded cascodes. I have outlined how their impact on offset and voltage noise can be minimised, and shown that the noise performance of an amplifier using the new transimpedance stage may even be superior to prior implementations; that is because of reduced current mirror noise contribution. There is a complexity penalty associated with the new circuits, compared to the standard amplifier implementation. However, there is no significant cost increase to be expected, as just small-signal transistors and standard passive components are needed. Also the increased quiescent current is usually of no relevance within the context of a full power amplifier design. I must leave the design of a fully worked out power amplifier design, using the new concepts presented here, to future research. However, the interested reader will find it easy to derive his own implementation from the presented model amplifier. If, as suggested in section 7, voltage regulators for the amplifier front-end are used, the design from figure 12 will only need minor modifications in the folded cascodes of the transimpedance stage to accept high voltage power supply rails. With the addition of a suitable power output buffer, and the necessary control and protection circuitry, a complete power amplifier is realised. To the best of my knowledge this new amplifier topology is first officially published in this article. However it is not possible to investigate all prior art, particularly all the information buried within the extensive patent repository. I shall be happy to hear about any findings with this respect from my valued readers. In Part 4: Appendix: Noise in folded cascode stages. 11. Acknowledgements
I'm very grateful to Bob Cordell for reviewing this text and for providing valuable thoughts on it. I'd like to express my thanks to Jan Didden for his efforts in publishing this article and for providing us with an excellent resource on audio electronics. References
[1] Douglas Self: Audio Power Amplifier Design Handbook, 5th edition, Focal Press, 2009
[2] Bob Cordell: Designing Audio Power Amplifiers, 1st edition, McGraw-Hill, 2010
[3] J. E. Solomon: The Monolithic Op Amp: A Tutorial Study, IEEE J. Solid-State Circuits, vol. 9, no. 6, pp. 314–332, December 1974
[4] Bhupendra K. Ahuja: An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 629–633, December 1983
[5] Samuel Groner: Comments on Audio Power Amplifier Design Handbook by Douglas Self, February 2011, available for download from www.sg-acoustics.ch/analogue_audio/power_amplifiers/pdf/audio_power_amp_design_comments.pdf
[6] Bruno Putzeys: The F-word - or, why there is no such thing as too much feedback, Linear Audio, vol. 1, pp. 112–132, April 2011
[7] Royal A. Gosser, Jeffrey A. Townsend: Integrated-Circuit (IC) Amplifier With Plural Complementary Stages, US Patent 5,537,079, filed December 1994, issued July 1996
[8] Giovanni Stochino: Ultra-fast amplifier, Electronics &Wireless World, pp. 835–841, October 1995
[9] Alberto Bilotti: Noise Characteristics of Current Mirror Sinks/Sources, IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp. 516–524, December 1975
[10] William H. Gross: New High Speed Amplifier Designs, Design Techniques and Layout Problems, Analog Circuit Design: Operational Amplifiers, Analog to Digital Convertors, Analog Computer Aided Design, Springer, 1993
[11] William F. Davis, Robert L. Vyne: Design Techniques for Improving the HF Response of a Monolithic JFET Operational Amplifier, IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 978–985, December 1984
[12] Graeme John Cohen: Double Balanced Microphone Amplifier, AES preprint, no. 2106, August 1984
[13] Bruno Putzeys: High-Performance Discrete Building Blocks for Balanced Audio Signal Processing, AES preprint, no. 6294, October 2004 About the author
Samuel Groner was born and currently lives in Zurich, Switzerland. He has been passionate about both art and science as long as he can remember. At present he works for Weiss Engineering Ltd. in the field of analogue hardware design and freelances as classical recording engineer/producer. Besides this, he teaches several courses at a local sound engineering school (ear training, classical music production and audio measurement) and enjoys a manifold activity as pianist, singer and choirmaster. If time permits, he is found on one of the numerous Swiss hiking trails, preferably in company with one of his cameras and a few sheets of black-and-white film. He holds a MSc degree in computer science and a MA degree as Tonmeister (recording engineer/producer).
This article originally appeared in Linear Audio Volume 2, September 2011. Linear Audio, a book-size printed tech audio resource, is published half-yearly by Jan Didden.
For more articles like this and others related to audio design, visit Audio Designline and/or subscribe to the monthly Audio newsletter (free registration).
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pcsalex
10/25/2012 7:18 AM EDT
Figure 12, Q9 and Q10 collectors shorted!
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pcsalex
10/25/2012 7:21 AM EDT
sorrry figure 12 Q9 and Q10 base are shorted ?
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ZekeR
11/2/2012 5:04 PM EDT
It's okay. Q9 and Q10 minimize the stage's crossover distortion. Their bases are meant to be connected.
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Fabio007
11/5/2012 2:48 AM EST
Q9, Q10 with collectors together and to gnd, and bases together: Yes I can see that these just buffer the signal (current) at Q5 collector before reaching Q11 Q12, however I would feel more comfortable it they operated with some voltage across their respective CB junctions - at least the SPICE modelling would be more accurate, I think; plus the Ft should be better (higher), so maybe those feed-forward capacitors C4, C5 could be smaller. A Vbe multiplier (or diode string) between collectors of Q5 and Q8 (with bypass capacitor) would be just fine for this, so that Q9 and Q10 both operate with Vcb of about 2V. This would not affect Q11 and Q12 except for reselecting bias resistors R13, R14.
Also I note there is just one diode string for the bias voltages for the output stage and input stages. This means signal (and load) current modulation of the base currents of Q15, Q16 will affect currents flowing in bias diodes D1 to D10, which will then affect the other stages.
Question: is there a reason the bias voltage for input stage (Q3, and Q4, Q5) is higher that of the output stage Q15, Q16 (5 diode drops vs just 2), or is this an attempt to reduce the aforementioned bias voltage modulation without resorting to separate bias networks and their associated increased bias current?
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Fabio007
11/7/2012 5:53 AM EST
This is a good topology; it has nice features (like the signal remaining a current right up until being converted to a voltage by a well-biased common-base stage that can charge/discharge capacitances rapidly). However, I’m not so sure the comparison of the “amplifier with new trans-impedance stage” in fig 12 with the “standard 2 stage topology” of figure 11 is entirely fair.
The amplifier of fig 12 has an extra transistor providing gain compared to the amplifier of fig 11. In Fig 12 the current signal output of the differential stage (the folded cascade stage does not amplify, it only provides a level-shifting function) is amplified by TWO transistors: both Q9 and Q11. This amplified current then gets converted to a voltage by the common-base amplifier stage Q15. This is three (3) transistors in total providing the gain of the output signal from the differential stage. Compare this with figure 11. Only Q6 and Q7 (forming a trans-impedance amplifier) amplify the output of the differential stage.
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Fabio007
11/7/2012 5:53 AM EST
Further, in Fig 11 the output stage is not complementary (push-pull) driven as is the case in Fig 12. In fig 11 Q7’s collector is loaded by a standard constant current source formed by Q9. In fig 12, Q10, Q12, form the complementary driver for Q16; there is no such complementary driver for Q9 in Fig 11.
Note also the extra bias current of fig 12, where Q9 is biased at 1mA, Q11 at 6mA, and Q15 at 7mA. Whereas in fig 11 the trans-impedance stage has bias currents of 1mA for Q6, and 6mA for Q7; there is no third stage biased at a current close to that of Q7.
Looking at transistor count: Fig 11 has a total of 11 transistors. Fig 12 has a total of 18; the extra 7 transistors are due to:-
a) folded cascade level shifter (3 extra if we include Q6);
b) one extra gain transistor (Fig 12s Q11)
c) three extra for the complementary driver (Fig 12s Q10, Q12, Q14).
For a fair comparison pitting purely topology against topology, perhaps it would be fairer to throw an extra 7 transistors at Fig 11 (say, by adding an extra gain transistor between Q6 and Q7 biased at about 6mA, and then add a complementary driven load for collector of Q7), and then seeing how they compare.
If that is done, then it may well happen that the amplifier of Fig 12 may still come out ahead for the measurements of interest (THD +N, and power supply ripple rejection); but I suspect the difference may not be all that great.
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