3-D requires system rethink

The rising interest in system-in-package combina- tions of memory and logic ICs is paving the way for a more complex form of 3-D integration: through-via interconnects. Although skeptics argue that problems related to cost, thermal load, electromigration and design complexity could keep such 3-D solutions on the back burner indefinitely, optimists are confident that breakthrough chips with through-via interconnects will arrive over the next few years.

Through-via interconnections are formed by etching or laser-drilling holes directly through chips and then filling the via holes with metal to connect the top chip to the lower one. The use of such connections can reduce the physical area of the chip stack and shorten the interconnect distance between the logic function on one chip and the logic block on a second chip. The shorter distances, in turn, shorten signal delays and thereby speed overall operation.

Vertical chip-stacking solutions should be thought of as a continuum, counsels Bob Jones, manager of system interconnect solutions at Freescale Semiconductor Inc. Some applications might call for existing designs connected through perimeter bond pads, creating a space-saving, "minimal footprint" vertical stack. Other applications call for "a rethink of the architectures" of the conjoined devices, using dense through-via interconnects, Jones said.

"For some applications, we can still go quite a way forward by using bond pad connections and remapping into a 3-D solution," he said. "The next level is to use global interconnects without redefining the chips. As we move forward with 3-D, we get into a redefinition of the architectures."

Indeed, several companies have implemented 3-D technologies at various levels of complexity. MtekVision Co. Ltd. (Seoul, South Korea) has used vertical connections and wafer-level processing techniques to create what it claims is the smallest camera control processor around, reducing the footprint by about 40 percent. Luxtera Inc. (Carlsbad, Calif.) has used vertical interconnects to create an all-silicon optical modulator solution for 10-Gbit/second transport. And Samsung Electronics, in a technology demonstration, has used laser drilling to create fairly large vias to connect no fewer than eight NAND flash memory chips.

Interest is brewing worldwide. At the Symposium on VLSI Circuits in Honolulu in June, Kenji Takahashi, a manager at Toshiba Corp.'s advanced packaging engineering group, described a low-cost Toshiba 3-D process that uses laser ablation to burn vertical holes for copper-plated, 10-micron vertical interconnects. The technology demonstration centered on an image sensor used in space-restricted mobile systems. The company has figured out how to use laser drilling without damaging the silicon, Takahashi said, although the active elements must be kept 10 microns or more from the surface of the vias.

Asian efforts
In a plenary speech at the symposium, Takahashi outlined about a dozen 3-D packaging R&D efforts in Japan, Singapore and other Asian nations. A Japanese-government sponsored effort with NEC Electronics, Oki Electric and other partners is putting together a DRAM using 3-D connections. The approach divides the memory array and supports error-correction code (ECC) and address circuitry on different dice.

At International Sematech (Austin, Texas), a small program to study the infrastructure needs of 3-D chips is being headed by Sematech's Susan Vitkavage under the direction of Sitaram Arkalgud, a Freescale assignee who manages Sematech's interconnect program.

"The No. 1 business issue concerning 3-D is the unclear cost/benefit situation," Vitkavage said. To that end, Sematech is developing a method to study the trade-offs of taking a 2-D chip into the third dimension, including wafer-on-wafer and die-on-wafer approaches.