Shift in the integration equation

The trend of the semiconductor road map has always been to pack more functions on a single die through process shrinks and better processing, bolstered by a larger die itself. This is especially true on the digital side, where economies of scale are easily defined: early CPUs soon expanded to include various types of I/O, buffers, memory and more. But it has also been true on

the analog side, as the "complete" 12-bit D/A converter led to the "really complete" DAC with integrated output buffer and then the "really, truly complete" DAC with internal voltage reference.

At a recent meeting with a leading linear-IC vendor, however, engineers noted that chip-scale packaging (CSP) technologies may be upsetting this IC road map axiom.

With CSP, the package is, in effect, the die itself, and there is little or no footprint penalty associated with smaller-scale levels of integration. In the CSP environment, a limited-function, smaller IC may hit a different sweet spot in terms of size, performance and time-to-market than a larger one. Though designers may still want to pack as many functions as possible into the design, they may not be able to do so, since pad pitch and die perimeter constrain the number of chip I/O lines.

There are other benefits to putting less functionality on chip, as long as there is no overall footprint penalty--that is, when the aggregate of single-function CSP ICs is not larger than a single die with all those functions. By incorporating only a few blocks or functions per die instead of squeezing everything in, vendors can select individual process technologies that are optimized for that block's function, rather than compromise across the various functions. For example, you could use one process optimized for a low-noise front end and a separate one for the high-voltage output driver of an audio channel.

Ironically, back in the day, vendors often used a combination of ICs on a common substrate and called it a hybrid device, to better match disparate semiconductor processes (such as analog, digital, precise, fast or stable) with the needs of the individual functional blocks. Today, such hybrids still own a niche within a niche of the electronic component world, but it's a very small one.

As a further benefit, the market risk of only a few functions per IC may be lower. The more highly integrated devices often target specific markets--and sometimes even single customers--but have less applicability elsewhere, whereas the smaller devices may be viable across a wider range of users who can pick and choose just those features they want and leave out the ones they don't.

What's more, the vendor's technical risk increases along with IC functionality.

As the technology wheel advances, engineers often need to reassess the assumptions that have served them well for years. With the growth of chip-scale packaging, we may be going "back to the future," with fewer functions per IC for system partitioning.