Under the Hood: Designers boost DRAM efficiency

Recent analysis of some of the latest DDR2 and DDR3 DRAM devices from leading manufacturers has revealed a couple of interesting trends. DRAM manufacturers, responding to harsh DRAM market conditions, are now offering more-efficient designs for both the mainstream DDR2 market and the next-generation DDR3 market.

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Semiconductor Insights (SI) reported DDR3 analysis results based on some of the early products of Micron, Qimonda and Samsung. According to the analyses, published on May 7, 2007, and Sept. 3, 2007, the overhead of enhanced speed and low power consumption of DDR3 over DDR2 was between 22 percent and 23 percent in the 90-nm and 80-nm process nodes.

A comparison can be made based on Samsung and Qimonda DRAM data with 80-nm and 90-nm processes, respectively. Cell efficiency for DDR3 designs ranges from 33 percent to 45 percent, but cell efficiency for DDR2 designs of the same process technology is much higher (from 41 percent to 54 percent). A wide internal data bus and its related circuitry, including data read/write amplifier and multiplexing circuits to support 8-bit prefetch architecture, consume precious silicon area. Extra pipeline stages to support high-speed I/O operations and improved on-die termination (ODT) circuitry, as well as other features introduced in the DDR3 standard, contribute to this die size overhead.

With less than the highest possible operating frequency (1.6 GHz) and a steep premium, and with performance-enhanced DDR2 parts on the market, DDR3 DRAM made little progress in 2007.

One DRAM manufacturer's reaction to this situation is noteworthy. The latest Micron DDR3 DRAM analyzed by SI shows the smallest DDR3 chip size--one very comparable to that of DDR2.

Die photo of Micron DDR3--SI# 19770

Die photo of Micron DDR2--SI# 19769

Die photo of Hynix DDR2--SI# 19359