The power of sequential design optimizations

Energy (or, more specifically, energy consumption) is at the forefront in everyone's mind these days. Whether we are sensitive to the cost of fuel, to the electricity bill or to a dead cell phone battery, our awareness of the energy we use has increased.

Mobile devices are at the heart of consumer electronics. These products are feature-rich, computationally intensive and limited by battery storage. In the last five years, the performance of mobile devices has increased by an order of magnitude, but battery capacity has improved only in small increments. The solution to bridge this energy gap must come from energy-efficient electronics.

Energy consumption in electronics is a function of power dissipation of the device and the applications running on it. In previous generations of devices, performance was the primary concern for designers. With a shift toward energy efficiency, the challenge is how to minimize energy and complete the application in a reasonable amount of time.

The year 2006 marked the crossover point when semiconductor revenue from processors going into consumer devices surpassed the revenue from those integrated into PCs. This trend, along with continuing demand for energy-efficient electronics, has accelerated the need for low-power design. Power optimization can no longer be an afterthought: It is a mandatory design requirement for consumer markets.

Power optimization must be addressed at all levels of design, from system level to GDSII. Many power optimization tools operate during register transfer level (RTL) synthesis and at later stages. These automated tools make changes to the design, such as adding clock gating, substituting high-voltage threshold cells and synthesizing power-efficient clock trees. Working in the existing design flow, they require little change in methodology. Also, the optimizations are combinational and can be verified by combinational equivalence checkers. Although these tools are necessary for 90-nm designs and below, they are not sufficient to create the most energy-efficient designs possible.

By working at higher levels of abstraction and making sequential changes, additional power savings are possible.

For example, understanding the interaction between application and architecture may make it possible to save power by running computations in parallel at half the frequency. Micro-architectural changes have a greater potential for saving power than do optimizations done at the gate level and below. However, micro-architectural optimizations are often difficult to implement, and because they change the sequential behavior of designs, they cannot be verified by combinational equivalency checkers.

A successful low-power design strategy ensures a cumulative reduction in power while taking into account timing and area requirements. The relationship between power, timing and area is not always intuitive. Because power optimizations push more signals toward negative slack, they can cause timing violations. Consequently, some power optimizations will end up being re-implemented or backed out. This creates a catch-22. Higher levels of abstraction offer a greater potential for saving power but have less accurate design information. While design information at the gate level is very accurate, its potential for saving power is limited. The solution is optimizing power at the RTL.

RTL clock gating

Clock gating is the most common RTL power optimization. It reduces dynamic power consumption by adding combinational logic into the clock path of registers, stopping them from propagating values to downstream logic. By applying clock gating, the functionality of the design remains unchanged and switching activity is reduced. The amount of power saved depends on the enable logic added and how long the registers are gated (turned off). The latter is a function of the switching activity for an application.

There are two types of RTL clock gating: combinational and sequential. Combinational clock gating translates a conditional statement in the RTL code into a clock-gating cell in the clock path of a register. Clock gating is automated by power-aware synthesis tools.

Sequential clock gating leverages inefficiencies in the RTL code, such as unused computations and data-dependent functions. Examples include observability-based optimizations that take advantage of data written to registers unused in subsequent clock cycles and stability-based optimizations that recognize when data is not valid from previous cycles. Both cases require multicycle functional analysis to identify sequential conditions as optimization candidates.

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