Design Article
Design RFICs with greater speed, accuracy
Kurt Johnson, Cadence Design Systems Inc.
11/22/2006 12:30 AM EST
The requirements of existing communication standards differ in terms of center frequency, signal bandwidth, SNR and linearity. This will considerably affect all radio front-end building blocks. A comprehensive trade-off analysis is also needed to select the most appropriate architecture and meet the individual circuit-block requirements.
The complexity of digital signal processing is also steadily growing. Digital blocks can compensate for some of the signal impairments caused by analog front-end blocks.
To verify complicated digital compensation algorithms and the effect of analog non-idealities such as phase noise, nonlinearity and mismatch, the analog and digital blocks need to be simulated together. A key bottleneck in RF/baseband codesign is the presence of the RF carrier signal at several gigahertz in the RF front end.
Simulating the bit error rate (BER) or package-error-rate (PER) of a complete telecom link at the transistor level—running thousands of cycles of the modulated signal—is very expensive and often impractical.
Design hurdles
Aside from this performance verification, where the actual design is
validated against specification, another key requirement is the
functional verification of the entire chip.
Simple implementation errors at the interface between the digital control circuitry responsible for various operating modes (e.g. power up, power down, receive, transmit and band selection) and the analog front-end are often the cause of expensive respins. IC designers typically overcompensate and stick to budget requirements passed down from the system designer.
The IC designer could prove that a more relaxed specification within the IC will still meet system-level requirements. However, with no way to prove the theory, time is spent optimizing circuitry that may not be necessary.
Systems involving baseband and analog/RF portions have traditionally been designed, simulated and verified separately due to the different mindsets of the engineers and the tools of the two domains. The goal during system-level design is to find an algorithm and architecture that implement the required functionality while providing adequate performance at minimum cost.
RFIC designers also face several significant challenges during the actual implementation phase. With a large IC such as a wireless transceiver, high-speed requirements make circuits extremely sensitive to parasitics, including parasitic inductance, passive modeling and noise. Thus, the essence of the RFIC flow is the ability to manage, replicate and control post-layout simulations and effects, and efficiently use this information at timely points throughout the design process.
Complete solution
RFIC design also requires specialized and unique analysis techniques
specific to RF design. These are a cross between frequency domain and
time domain analysis methods, which are chosen on the basis of either
circuit type and type or designer preference and comfort level.
Ultimately, this requires a seamless environment that affords a choice
of simulation method.
Integration trends have also affected the RFIC world, which used to be viewed as a separate, almost standalone entity. Today, many RFICs contain at least the ADC, DAC and PLL functions, as well as a digital synthesizer that is created through the digital environment and integrated on chip.
In other cases, RF content is being added to large SoCs as some design groups attempt a single-chip solution. Still others are integrating by using system-in- package (SiP) techniques, which results in the same verification issues confronting RFIC and SoC methodologies.
Addressing these challenges requires a complete solution that must:
1) Provide comprehensive
links between system-level design and IC implementation;
2) Enable IC verification
within a system-level context to leverage existing wireless libraries,
models and testbenches;
3) Allow full-chip mixed-level
simulation at different abstraction levels (language neutral);
4) Allow for detailed analysis
at the block and chip levels at an optimized simulation time;
5) Manage and facilitate
simulation with full parasitics;
6) Contain layout automation
that can be used at appropriate points in the design; and
7) Allow for several levels of
passive modeling throughout the design process.
These requirements must be met through a single environment that not only facilitates the job of the RFIC designer natively, but also integrates with other domains such as AMS and digital.
This must include both a chip- and block-level perspective at multiple abstraction levels, where the same design collateral can be passed back and forth, thus facilitating verification and implementation from the environment's point of view, independent of physical integration strategies.
The first place to start describing an RF IC flow is from a more global methodology perspective and context.
The Advanced Custom Design (ACD) methodology in Figure 1, below describes a process geared towards mixed-signal design, which takes design tasks and parallelizes them, allowing for a top-level perspective, for parasitic and analysis functions performed early and often, and which ultimately enables the design to progress with as much information as is available at any given point in time.
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| Figure1. ACD methodology combines top-down approach speed and bottom-up accuracy. |
Predictability is the driving force behind the ACD methodology. The need for predictability is driven by two primary concerns: schedule, which must be met from the beginning of the design process, and which necessitates a fast path to tapeout; and performance requirements, which must be met to achieve first-pass success, and which require a silicon-accurate methodology.
Top-down, bottom-up
To meet schedule requirements, RF designers need a fast design process
that supports thorough simulation and physical design. The top-down
design process, when applied to both simulation and physical design,
results in a fast design process. The design process is comprised of
many tasks; many of today's chips contain multiple blocks from multiple
design domains.
Thus, it is imperative to design-in as many of these blocks and perform as many tasks as possible in parallel, leveraging as much of the top-level IP as possible throughout the process. This leads to the concept of design evolution, where all a design's IP is leveraged as it matures through the design process.
Using this concept, multiple abstraction levels—from high-level design through detailed transistor-level design—are combined to support a mixed-level approach that targets detailed design to only the points needed for a given test. This also enables designers to leverage top-level information for block design, and to subsequently re-verify the blocks in the top-level context.
To achieve the required design performance, RF designers need a silicon-accurate design process. Silicon accuracy relies on base design data, such as device models, that support accurate simulation, and technology files that support physical verification and analysis.
Test chips, which are often comprised of critical structures that are known from past designs to be highly sensitive, are also used in this process to verify the feasibility of a process and the accuracy of its corresponding process design kit (PDK). Often, a design group will need to add components to the PDK to support a particular design style.
Device models may need to be expanded to combine or add corners, or to facilitate statistical modeling or other approaches the design team requires.
This silicon-accurate data is driven through the design process through detailed transistor-level analysis, including layout extraction. The calibration of these lower-level silicon-accurate results to higher levels of abstraction ensures that designs will meet performance requirements. This comprises the bottom-up portion of the ACD methodology.
In practice, the top-down and bottom-up processes work in parallel, producing a "meet-in-the-middle" approach. This meet-in-the-middle approach balances the need for fast design processes with silicon accuracy, which ultimately produces a predictable schedule and leads to first-pass silicon success.
The ACD methodology can be applied to a complex integration or to a particular domain area. The methodology for each domain applies the meet-in-the-middle approach, combining top-down speed with bottom-up silicon accuracy.
Wireless flow
Figure 2 below depicts the
wireless RFIC flow. The flow targets the RFIC designer and spans system
design down to IC implementation, following the meet-in-the-middle
approach described earlier.
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| Figure 2. Wireless RFIC flow spans system design down to IC implementation, using a meet-in-the-middle approach. |
The design collateral from the system design process is used as the first and highest abstraction level. System-level descriptions become an executable testbench for the top-level chip. Models of the surrounding system can be combined with a high-level model of the chip, producing an executable specification.
System requirements serve as the first specification to drive the chip-level requirements, and ultimately turn into repeatable testbenches and regression simulations. Part of the leveraged system-level content is also the IP that determines the system relevant figures of merit, such as EVM, BER and PER.
Mixed-level simulation allows a natural sharing of information between the system and block designers. To enable the required links from the system environment to the IC environment, it is essential that the underlying multi-mode simulation solution is language-neutral (from system models in C/C++, SystemC and SystemVerilog to digital/mixedsignal/ analog behavioral HDL languages to Spice) and provides different engines and algorithms dedicated to the specific needs for a multidomain circuit design.
Successful execution on a complex design is contingent on thorough upfront planning. No design comes together smoothly by accident. With a strong initial plan that specifies which top-level requirements, block-level requirements and mixed-level strategies to use, a meet-in-the-middle approach can drive each block design to ensure full coverage of important design specifications and smoothly allow blocks to have different schedule constraints.
Therefore, the development of a comprehensive simulation strategy, which in turn leads to a modeling plan, is key. After realizing a high-level executable specification, the process continues by identifying particular areas of concern in the design. Plans are then developed for how each area of concern will be verified.
The plans specify how the tests are performed and which blocks are at the transistor level during the test. It is important to resist the temptation to specify and write models that are more complicated than necessary. Start with simple models and only model additional effects as needed.
A formal planning process generally results in more efficient and more comprehensive verification, meaning that more flaws are caught early and there are consequently fewer design iterations. The simulation and test plans are applied initially to the high-level description of the system, where they can be debugged quickly. Once available, they can be applied during the mixed-level simulations of the blocks, reducing the chance that errors will be found late in the design cycle.
Multimode environment
The top-down process starts with HDL modeling for the entire RFIC added
to the system-level testbench. This would include all RF blocks along
with any analog content and/or digital blocks.
The first step is to behaviorally model the full chip within a top-level testbench, which would verify some system tests such as EVM or BER. This at first verifies the partitioning, block functionality and ideal performance characteristics of the IC. This behavioral setup then serves as the basis to facilitate mixed-level simulations, where blocks can be inserted at the transistor level and verified in a top-level context.
This full-chip and system setup can serve as the regression template to allow for continuous verification as blocks mature, allowing for a continuous evolution approach through the entire design. This is important, as any problems that are found can be detected at the earliest moment where time still exists to fix the problem and blocks can be designed in parallel to individual schedules.
Looking through the full simulation environment, several views of the same circuit will exist. This is likely to consist of a behavioral view, a pre-layout transistor-level view and several views of parasitic information. As blocks mature, it may be necessary to add more transistor-level information to test RF/analog and RF/digital interfaces. This will require the use of a mixed-signal simulator capable of handling analog, digital and RF descriptions, and mixed behavioral-level with transistor- level abstractions.
Pick the appropriate views of each block or sub-block and manage the runtime vs. accuracy trade-offs through simulation options such as sending the transistors to a FastSpice simulator or keeping the transistors in a full Spice mode. This configuration is highly dependent on the circuit and sensitivity of the interfaces. The ability to manage these configurations effectively is vital, as these are required to be repeatable. This provides an effective mechanism to set up the continuous regressions that support the ACD Methodology.
A preliminary circuit design then takes place, allowing for early circuit exploration and a first-cut look at performance specifications. This early exploration leads to a top-level floorplan, which for RFIC is sensitive to noise concerns and block-level interconnect.
At this stage, it is possible to synthesize passive components such as spiral inductors to spec, and do an initial placement of them on the chip. This enables two key activities: creating early models for spiral inductors that can be used in simulation before the block-level layouts are complete, and allowing for an initial analysis of mutual inductance between the spirals. Component models of each inductor can be generated within this context for use in these simulations.
Simulation is performed using the designer-preferred method, either in the frequency or time domain. This depends on the circuit, type of simulation, or amount to be simulated, and is a judgment call by the designer.
A single PDK and associated environment allows for a smooth determination and selection of the simulation algorithm desired. Results are displayed through an appropriate display for the simulation type selected. As circuits are completed at block level, they are verified within the top-level context with behavioral stimulus and descriptions for the surrounding chip.
Physical implementation
Layout automation (automated routing,
connectivity-driven layout, design- rule- driven layout, placement)
can be used judiciously.
The advantage to layout automation is that it's tied to the schematic and DRC rules, and allows for productivity gains. Analog-capable routers can help with differential pairs and shielding wires, and allow for manual constraints per line.
This allows for a physical design process that is repeatable just like the frontend process. It may take some time and overhead to set up the initial tools, but this is made up as iterations are made through the design process. Engineering change orders (ECOs) are more effectively performed if a repeatable layout process is in place.
This is weighed against highly sensitive circuitry, which demands a manual approach. As layout is complete, electromagnetic (EM) simulation can be used to provide highly accurate models for passive components.
For example, several spiral inductors may be selected as highly critical and a target for EM simulation; these can be swapped by replacing the models that were created early in the design process, and mixed and matched with existing models. The designer then has full control over managing the spiral modeling process, again having the ability to trade-off runtime vs. accuracy at their discretion.
Net-based parasitic extraction becomes a key element of the process as layouts emerge. RF design is highly sensitive to parasitic effects. As such, the ability to manage different levels of parasitic information becomes paramount, as the designer can describe which areas, lines and blocks can have progressively more or less parasitic information associated with them.
Less sensitive interconnects may require RC only, whereas more sensitive lines may require RLC. For lines with spirals attached, these can be extracted fully with RLC plus the associated inductor component, even with substrate effects added for the most sensitive lines.
Again, the lines that contain a "full" extraction can be mixed and matched with the component models for passive components that were created earlier. In addition, as the top-level layout emerges, analysis - especially substrate noise -is used to ensure that noisy circuits (such as digital logic and perhaps PLLs) are not affecting the highly sensitive RF circuits.
Designers can check for this, and as they flag areas of concern, they can either modify the floorplan accordingly or add guardbands around the noisy circuitry. However, it is often impractical to both simulate the entire design at transistor level and include all the parasitic information.
One approach is to extract calibrated behavioral models using the extracted view of the design blocks. But this will not capture the effects of the parasitics on the interconnect between blocks. Thus, hierarchical extraction capabilities to extract only parasitics of the interconnect between design blocks need to be supported.
Calibrated HDL models
Finally, as blocks are completed, the initial behavioral models can be
back-annotated for key circuit performance parameters, which can
provide more accurate HDL level simulation.
While this will not account for every effect, it can add more realistic performance information at little runtime cost, allowing for faster-level verification and perhaps reducing the amount of full transistor-level verification. In this way, the verification of a block by mixed-level simulation becomes a three-step process.
First, the proposed block functionality is verified by including an idealized model of the block in system-level simulations. Next, the functionality of the block as implemented is verified by replacing the idealized model with the netlist of the block. This also allows the effect of the block's imperfections on system performance to be observed. Finally, the netlist of the block is replaced by an extracted model.
By comparing the results achieved from simulations that involved the netlist and extracted models, the functionality and accuracy of the extracted model can be verified. From then on, mixed-level simulations of other blocks are made more representative by using the extracted model of the block just verified rather than the idealized model.
When performed properly, bottom-up verification achieves detailed verification of very large systems. Behavioral simulation runs quickly because the details of the implementation are discarded while the details of the behavior are saved. Because the details of the implementation are discarded, the detailed behavioral models generated in a bottomup verification process are useful as blocks mature or for third-party IP evaluation and reuse.
Especially for wireless systems including RF front-ends, bottom- up verification is mandatory when verifying the performance of large systems. As mentioned earlier, RF system simulations at the transistor level (running thousands of cycles of the modulated signal) is often impractical.
The use of advanced envelope analysis techniques instead of traditional transient simulation would only provide a speed-up by a factor of 10-20x. And even bottom-up extraction using traditional passband models, where the RF carrier is still present, won't provide the required speed-up. Only the combination of bottomup model extraction techniques with so-called complex baseband or low-pass equivalent models (where the carrier signal is suppressed) will lead to simulation times that enable PER analysis at the full-chip level.
Generating behavioral models that include the detailed behavior of even simple blocks can be difficult and requires a specialized skill not commonly found in the design team. Thus, the team needs automated tools and methodologies that generate detailed behavioral models with verified accuracy, and an open API to modify existing templates according to specific application and/or technology needs.
Kurt Johnson is Group Director, Cadence Verticals, Cadence Design Systems Inc.
To read a PDF version of this story, go to "Design RFICs with greater speed, accuracy."
