PRODUCT HOW-TO: Optimizing GPS, Audio/video streaming algorithm designs with Atmel's customizable CAP MCUs

Various applications, ranging from GPS to audio/video stream processing, require complex algorithms to be executed in real time. Many of these algorithms follow industry standards that are upgraded periodically.

Engineers who are developing such applications are facing a challenge: to optimize the execution of these algorithms within the tight constraints on the unit cost, physical size and power consumption of the device that is often manufactured in high volume, and strict limits on the cost and development time. The end product must be able to be adapted to upgrades in the processing algorithms at a reasonable cost.

For optimum algorithm execution, the basic rule of thumb is hardware for performance and software for flexibility. In practice, this rule is difficult to apply. Hardware choices are limited to the basic arithmetic functions of the MCU core, the multiply/accumulate and linear function processing of a DSP core, or the wider flexibility of an FPGA with its downside of physical size, power consumption and unit cost in volume.

The alternative of a standard-cell ASIC can give a higher level of performance, but at a development time and cost that is often prohibitive. Software is ported onto the MCU or MCU/DSP combination that has been selected for the hardware implementation.

Once the hardware/software (HW/SW) partitioning has been made, altering it is extremely difficult and time-consuming, unless the application will go into volume based on an FPGA. Often, it is only in the final stages of application development that the software can be run on the target hardware and when it can be determined whether the implementation of the processing algorithm is optimal.

Implementation flow
Atmel's CAP comprises MCU-based SoC that provides the basic processing capacity and a highdensity block of metal-programmable (MP) digital logic that can be personalized to provide DSP-like or other dedicated function execution hardware.

It provides a reasonable development cycle time and cost. The development flow for an application-specific CAP includes an emulation step based on a development board that uses a high-density FPGA to emulate the algorithm execution functionality that will subsequently be hardened into the MP block.

CAP enables an application developer to get the best of the FPGA and ASIC worlds. The first phase of the CAP application development cycle uses FPGAbased libraries and tools. This is to make an initial HW/SW partition of the algorithm and then map the hardware-based functions onto DSP-like structures or other processing elements implemented in the FPGA.

In parallel, the software-based algorithm processing is compiled for execution by the MCU that sees the FPGA/MP block in its address space, with a distributed DMA architecture to optimize data flows between the functional and memory blocks.

Figure 1: HW/SW partitioning involves implementing an algorithm using a library of IP blocks containing hardware modules and their associated software drivers.

Figure 1 above shows the overall steps of the HW/SW partitioning and implementation of an algorithm using a library of IP blocks that contains both hardware modules and their associated software drivers.

On the hardware side, the algorithm modules are first synthesized using tools available from the IP library or FPGA supplier. These are then synthesized with the required DSP or similar function processing blocks from a library provided by the FPGA supplier. The final step is to map these high-level constructs onto the basic FPGA structure to configure the FPGA in the CAP development board.

On the software side, the IP blocks required for the algorithm are compiled, and then linked with Atmel's library of low-level device drivers that handles the detained operation of the multiple peripherals and external interfaces of the CAP SoC. If required, this code is then linked to the OS, user interface and top-level control modules for the operation of the entire system. The complete code set is loaded into the program memory for the MCU core, which is the central architectural element of the CAP.