Reducing Power in Embedded Systems by Adding Hardware Accelerators

The rule of thumb in embedded system design has been that adding hardware increases power demands. The careful use of hardware accelerators, however, inverts the rule: adding hardware can reduce power.

By analyzing algorithms and implementing appropriate accelerators in programmable logic, developers can increase a design's performance while reducing power consumption in an embedded computing system.

Test results show that accelerators extend tradeoff options from as much as 200-fold performance improvement for the same power to the same performance with a 90% power reduction.

Programmable logic has, somewhat undeservedly, maintained a reputation from its early history as being a power-hungry approach to logic design. The rules of thumb have been that power consumption in an integrated circuit is roughly proportional to the chip's area for a given process technology, and a design implemented in programmable logic tends to be larger than if implemented in hard-wired logic. But these two factors, although suggestive, are misleading.

Far more significant than area-related power dependency is the frequency-related power dependency of an integrated circuit. Because CMOS circuits draw most of their current when transistors switch states, the frequency at which a circuit operates has a much greater impact on power consumption than simple chip size.

The higher the frequency, the greater the power demand. This opens the possibility that designers can reduce chip power consumption by adding circuitry, if the result of adding hardware is a significant reduction in clock speed.

For years, embedded processors have relied on custom hardware functions to accelerate common algorithms such as graphics or signal processing to accomplish more work per clock cycle. While this approach increases system performance, it does not reduce the system clock or dynamic power consumption. If hardware can be applied to accelerate software algorithms AND reduce the clock frequency, power can be saved while meeting system performance.

Not all functions are equally well suited to trading circuits for frequency, however. Sequential processes, where one step must be completed before the next begins, typically see little benefit from added circuitry.

Functions that can operate in parallel, on the other hand, can run much faster when hardware is available to execute several steps simultaneously. This translates into greater performance for a given clock speed, but also into a lower clock speed for a given performance level. Thus, the addition of hardware to a chip design can lower power demands while maintaining performance.