Multiple A/Ds versus a single one: pushing high-speed A/D converter SNR beyond the state of the art

(Note: an edited version of this article appeared in Planet Analog magazine, June 24, 2007. This online version includes formulas and derivations that did not appear in the print version.)

The wireless communications field is constantly demanding faster and higher resolution high-speed data converters to enable them to process more bandwidth (allowing more channels) with greater resolution. One way to further advance state-of-the-art analog-to-digital converters (ADC) is to average multiple high-speed ADCs to increase the dynamic range. With two ADCs, for example, the overall signal-to-noise ratio (SNR) can be improved by up to 3 dB; with three converters, it can be as much as 4.8 dB.

Theoretically, the SNR can be increased by 3 dB (one-half-bit) with two different methods. One option is to double the sampling rate and digitally filter the output (e.g., with an FIR decimation filter). The second option is to parallel two ADCs and simply average the digital output. At times, doubling the sampling rate is the less desirable option because faster ADCs may not yet be available. They may also start out with a lower SNR and often times are higher power than two slower ADCs. Furthermore, a faster sampling clock with low jitter is required.

This article shows the actual results of combining three TI ADS5546 converters (14-bit, 190 Msps), using the second option of paralleling the ADCs, and it addresses the clock jitter requirement which engineers face with the implementation.

Setup
The concept of averaging the output of separate ADCs for SNR improvement was verified using three ADCs tied to an FPGA, which then outputs the conversion results of each individual ADC or two or three ADCs averaged together, Figure 1. By using three ADCs instead of one, the SNR ideally improves by 4.8 dB, as derived below, which boosts the 14-bit ADC (SNR ∼74dB) to a 16-bit ADC level (SNR ∼79dB).

The analog input signal was split and fed into three ADCs which were sampled with a common clock source. An FPGA performed the averaging function as well as a level translation of the digital output from DDR-LVDS to LVTTL (double-data-rate, low-voltage differential signal to low-voltage TTL).

Figure 1: Block Diagram of System to Average Multiple ADC Outputs
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The averaging technique reduces uncorrelated white noise, but has no effect on distortions inherent to the ADC design that might be common to all three ADCs. If, for example, the ADC creates a large third-order distortion product, it will show up in each ADC used and averaging won't reduce it. Therefore, averaging only improves SNR, but not spurious free dynamic range (SFDR).

The formulas and derivations used to determine the maximum SNR gain for the two methods described above (doubling the sample rate and averaging multiple ADCs) are discussed in the addendum at the end, "Theory."

Measurements
In order to verify the SNR gain, a board was designed containing three ADS5546 ADCs (14-bit, 190 Msps) and an FPGA that was used to perform a 3:1 averaging function. Using two or three standalone ADC evaluation modules (EVM) for this experiment usually doesn't work as well, because noise coupled into the cable assembly is correlated and, therefore, doesn't average out. Furthermore, if the cables are not matched very well, skew between ADCs adds phase mismatch and further degrades the overall SNR.

Unfortunately, the chosen input matching network design was not optimized. The trace impedance was not adjusted properly to the transformer and the split input traces were not properly matched. Due to this input mismatch, the input signal was attenuated at frequencies above 60 MHz with one exception. Around 150 MHz, the input circuitry seemed to work very well. Therefore, some of the measurements were taken with an input amplitude as low as -6 dB, and were mathematically adjusted to -1 dB full scale (FS) afterwards in the following manner.

First, with only one ADC active, the SNR performance was measured and compared to the ADS5546 data sheet performance at the lower input amplitude. Then the measurement with three ADCs active was adjusted by the difference. This adjustment seems justified as the 150 MHz data point is right in line with the resulting values, Figure 2.

Figure 2: SNR Comparison between ADS5546 Data Sheet Values, Single ADC and Triple ADC
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The adjusted measurements show a consistent 4-or-greater dB improvement across various input frequencies when comparing it to 'single ADC' data. Even at the higher input frequencies, the measured and calibrated values within one-half dB of the theoretical values with the exception of device number three. The noticeable SNR roll-off is due to the clock-jitter limitation which is prevalent in any ADC, as derived in the next section.

Clock jitter requirements
The final SNR at the output depends on the input frequency and is primarily limited by the thermal noise of the ADCs and the aperture jitter of the sampling clock.

As derived earlier, averaging the SNR of three ADCs improves all uncorrelated noise sources by ∼4.8 dB which applies to the thermal noise term, as well as the internal aperture jitter of the ADC.

The ADS5546 data sheet lists the following specifications:

• Thermal noise ∼74 dB (=SNR at low input frequency where SNR is thermal noise limited)
• Aperture jitter ∼150 femtoseconds (fs)

Therefore, when averaging the outputs of three ADCs sampling the same signal, the overall thermal-noise contribution is reduced from 74 dB to 78.8 dB and the ADC aperture uncertainty from 150 fs to 86 fs (1.50 fs · 10^-4.8/20).

The sampling jitter comprises the internal aperture jitter of the ADC and the jitter of the external clock source (common to all three ADCs when averaging).

Using this combined clock jitter value, the resulting ideal SNR at a given input frequency can be calculated as following, where f_IN is the input frequency:

Figure 3 shows this SNR limitation due to clock jitter alone.

Figure3: Theoretical Possible SNR Limited by Clock Jitter
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Since thermal noise and internal aperture jitter are fixed values, the final SNR number is dictated by the quality (jitter amount) of the external clock source.

Next, the theoretical SNRs when using one and three ADCs were calculated and compared against the measured values, Table 1.

Table 1: Results of test; SNR_Jitter is converted to dB FS: SNR[dB FS]= SNR[dBc]+1 (at -1 dB FS)
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Since the signal generator and cable contain about 70 fs clock jitter, the total clock jitter is:

• ∼170 fs (one ADC with 150 fs ADC aperture uncertainty)
• ∼110 fs (three ADCs with 86 fs ADC aperture uncertainty)

The measured SNR values come very close to the predicted SNR values up to frequencies ∼200 MHz. This shows our formulas are well suited for a first order approximation.

Following are some examples to estimate the phase-noise requirement of the external clock source.

(Click to enlarge image)

This article shows how averaging the outputs of multiple high-speed ADCs can be used to improve data converter SNR. While an alternate technique of oversampling the input signal using faster ADCs is possible, the averaging approach seems preferable because faster ADCs which enable oversampling may not be available, and lower-speed ADCs used in an averaging approach may have better initial SNR specifications and lower power. This article examined the averaging approach.

Hardware was built to measure the SNR performance of using two and three high-speed (190 Msps) ADCs to sample an input signal in parallel. We found that special care must be given to the impedance transformation of the input matching circuit, as a lot of signal attenuation and distortion can be caused by the impedance mismatch.

Characterization of the system showed that noise in these high-speed converters is dominated by uncorrelated white noise and averaging multiple converter outputs does effectively improve SNR in a near ideal way in these controlled conditions. As expected, the SNR of the system decreased as the input signal frequency was increased. The reason is that the clock signal jitter affects the aggregate SNR of the system, and the SNR reduction is dependent on the input signal frequency. This paper analyzed the effects of jitter internal and external to the ADCs, finding close agreement between experiment and theory.

In summary, averaging the outputs of multiple ADCs can be used to improve state-of-the-art data converters. ADCs with low internal aperture jitter help maximize the SNR gain. With proper care taken with the input matching circuit and clock jitter, the SNR gains can match the 4.8 dB improvement predicted by theory when averaging three ADCs.

Theory

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Additional information can be found at the following websites:
www.ti.com/analog
www.ti.com/dataconverters
www.ti.com/sc/device/ads5546

About the Authors
Grant Christiansen is an Engineering Manager at Texas Instruments, where he is lead for the signal-chain and digital power applications teams. He has four patents in read-channel applications and earned his MSEE from the University of Minnesota.

Thomas Neu is a Field Applications Engineer for Texas Instruments, where he provides customer support with system and circuit designs. He received his MSEE in RF/Communication from Johns Hopkins University.