The previously explored analog-to-digital converters (ADC) (Part 8 and Part 9) are based on either a linear interpolation (flash) or a binary-search tree (pipeline and SAR). The delta-sigma converter is a primitive, one-bit ADC operating at a very high sample rate which averages the results over a large sample, to obtain a high-resolution result. The digital representation of the input signal is determined by the percentage of ones in the high-speed bit stream. This is accomplished by a circuit called a decimation filter to determine the final conversion value.

This circuit is called either the delta-sigma or the sigma-delta converter. However, the delta-sigma name has gained wider acceptance because it describes the sequence of operations. The heart of this converter is the modulator (Figure 1).

Figure 1: Delta-Sigma Modulator
(Click on image to enlarge)

All of the converters previously discussed have been open-loop systems. The delta-sigma modulator is a closed-loop system which maintains the average number of digital ones at the output equal to the input signal's percentage of full scale. Consider the series of events as the loop continuously searches for equilibrium.

• As the modulator starts, the integrator output is low so the comparator sets the DAC output to Vref, and sends a one to the data stream. Note that this is just the first bit sent to the next stage, and may not be the MSB of the final data word.
• The voltage applied to the integrator is the difference between Vin and Vref.
• If Vin is large, the signal applied to the integrator is small. Therefore, several samples must be accumulated at the integrator for its output to cross the comparator threshold.
• When the integrator output crosses the comparator switch point the next bit will be a zero, which causes the DAC to output a low voltage.
• This results in a large charge being subtracted from the integrator.
• If Vin is small, then the first charge on the integrator will be large. The voltage (Vref-Vin) will be big and a one placed on the output bit stream. It takes several low DAC outputs with the corresponding zero on the bit stream to balance the large initial charge on the integrator.
• The output comparator often is called a one-bit ADC.
• The comparator output is sampled and the DAC refreshed on a clock time base.

Deviation from an ideal PPM sequence is a form of noise in the modulator output. An integrator is a single pole, low-pass filter. Thus, the noise level can be reduced by adding a second integrator (Figure 2).

Figure 2: A second order Delta-Sigma Modulator
(Click on image to enlarge)

Because this is a closed-loop system, adding more input integrators can cause stability issues.

The modulators described above are followed by a digital low-pass filter, and then a decimation filter. These digital circuits establish the output data rate, which will be greatly different from the rate at which the input signal is sampled. The way these filters are designed determines the data latency. The time from a step change in the input signal to a stable digital output, reflecting that change, will always be a least one data cycle. Different filter designs require various numbers of data cycles to reach a stable output.

This technique shapes the conversion noise to the high input-sample frequency band, away from the frequency band of interest.

About the author



William P. (Bill) Klein is a Senior Applications Engineer with the High Performance Analog group at Texas Instruments. Bill joined TI through its acquisition of Burr-Brown in August 2000. His experience as an analog circuit designer covers over 40 years in fields ranging from mineral exploration to medical nuclear imaging. One current role Bill has is hosting the Analog e-LAB Web Cast, presenting real world solutions to real world problems in analog circuit design. In addition to a BSEE from Arizona State University and registration as a Professional Engineer in the State of Arizona, he has authored numerous magazine articles, application notes and conference papers.

Previous installments of this series:

• "SIGNAL CHAIN BASIC Series (Part 9): SAR Converter Operation Explored", www.planetanalog.com/features/showArticle.jhtml;?articleID=206901015, click here
• "SIGNAL CHAIN BASIC Series (Part 8): Flash- and Pipeline-Converter Operation Explored", www.planetanalog.com/features/showArticle.jhtml;?articleID=206504089, click here
• "SIGNAL CHAIN BASIC Series (Part 7): Op Amp Performance Specification--Bias Current", www.planetanalog.com/features/showArticle.jhtml;?articleID=206101908, click here
• "SIGNAL CHAIN BASIC Series (Part 6): Op Amp Input Voltage Offset", www.planetanalog.com/features/showArticle.jhtml;?articleID=205901111, click here
• "SIGNAL CHAIN BASICS Series (Part 5): Introduction to the Instrumentation Amplifier", www.planetanalog.com/features/showArticle.jhtml;?articleID=205208593, click here
• "SIGNAL CHAIN BASICS Series (Part 4): Introduction to analog/digital converter (ADC) types", www.planetanalog.com/features/showArticle.jhtml;?articleID=204803631, click here
• "SIGNAL CHAIN BASICS Series (Part 3): Analog and the digital world", www.planetanalog.com/features/showArticle.jhtml;?articleID=204400376, click here
• "SIGNAL CHAIN BASICS Series (Part 2): Op Amp--Basic operations", www.planetanalog.com/features/showArticle.jhtml;?articleID=203101699, click here
• "SIGNAL CHAIN BASICS: Operational Amplifier--The Basic Building Block", www.planetanalog.com/features/showArticle.jhtml;?articleID=202801320, click here