Multiple techniques solve stability problems in power op amps (Part 2 of 3)

Editor's note: this series consists of three parts:

• Part 1 looks at Bode Plots, power op amp behavior versus frequency, and a first-order check for stability, click here
• Part 2 looks at four compensating techniques, including phase, feedback zero, noise gain, and isolation resistor compensation, click here
• Part 3 provides examples of compensation techniques, including feedback zero, feedback zero and noise gain, compensation, click here

Four compensating techniques
Phase Compensation–In most treatments of stability, phase compensation will never come up because most small signal amplifiers are internally compensated and therefore there is nothing that can be done externally to modify the amplifier. However, in almost every high power op amp, the phase compensation can be controlled by an external capacitance (C_C) so that it can be user defined. This enables moving the first pole of the open loop gain (A_OL) plot left or right in frequency, as depicted in Figure 5.

By raising the value of C_C, the open loop gain (A_OL) plot can be moved to the left and down so that what would otherwise be a problem pole–a descent at 40 dB per decade–moves below 0 dB. Because this type of gain analysis always uses the non-inverting gain, the happenings below 0 dB are of no consequence.

Figure 5: Phase compensation
(Click on image to enlarge)

Feedback Zero Compensation–As depicted in Figure 6, feedback zero compensation is a method of tailoring the performance of a power amplifier for a given application. The goal is to employ a feedback capacitor (C_F), to alter the closed loop gain at higher frequencies by placing a pole in the 1/β plot so that it intersects the open loop gain (A_OL) line at 20 db per decade–instead of at 40 dB per decade. The 1/β plot angle of the intersection created by a properly place pole, is now 20 dB/decade. Hence it is stable. The usable bandwidth is approximately 2 kHz in Figure 6.

This technique is very sensitive to the tolerance and temperature stability of the feedback components because the loop gain (1/β) plot is governed by the RC response of the feedback. Therefore the power amplifier is very susceptible to moving in and out of stability based on capacitor (C_F)–which may change by as much as 5% to 20% in value with changes in temperature.

To summarize, this technique is easy to implement when the loop gain (1/β) value is large, but the technique is somewhat sensitive to variations in component values.

Figure 6: Feedback zero compensation
(Click on image to enlarge)

Noise Gain Compensation–Figure 7 illustrates how noise gain compensation functions. This technique adds a parallel Z_I path through R_I and C_I, as shown in Figure 7. The objective with this technique can be summarized by saying that it is aimed at closing the loop gain early.

One way to view noise gain circuits is to view the amplifier as a summing amplifier. Consequently two signals are fed into the inverting (-) port of the summing amplifier. One is VIN and the other is a noise source summed via ground through the series combination of R_I and C_I. Since this is a summing amplifier, V_OUT/V_IN will be unaffected if the sum is zero via the R_I-C_I network. However, in the small-signal AC domain, the 1/β plot of the feedback is changing. Consequently, as C_I becomes a short as the frequency rises, and if R_I << R_IN, then the noise gain will be governed by R_F/R_I.

Notice that in Figure 7 and Figure 8, when the capacitive reactance of C_I is large, then the 1/β ₁ line is governed by R_IN. However, when the capacitive reactance of C_I becomes small, then RI supplants RIN as the input resistor accounting for the shift to the 1/β 2 line which crosses the open loop (A_OL) line at 20-dB per decade. The usable bandwidth is approximately 800 Hz in Figure 8. The Noise Gain technique is largely immune to component tolerance variations. However, it is only appropriate for non-inverting, i.e., summing configurations, and it does sacrifice loop gain, and therefore accuracy at higher frequencies.

Figure 7: Noise gain compensation circuitry
(Click on image to enlarge)

Figure 8: Noise gain compensation plots
(Click on image to enlarge)

Isolation Resistor Compensation–In Figure 9, isolation resistor compensation is illustrated with resistor (R_ISO) connected in series with the load (C_L). As depicted in Figure 10, the 1/β line, if uncompensated, would intersect the open loop gain (A_OL) line–the dotted blue line–where the phase shift is 40 dB per decade so that the circuit would be unstable.

The resistor isolation compensation technique restores the 20 dB per decade slope to the Bode Plot amplifier gain plot, as shown by the red line in Figure 10. This is accomplished by inserting resistor (RISO) between the output of the amplifier and the capacitive load. This adds a corner frequency of zero in the open loop (A_OL) plot, restoring a 20 dB per decade slope before the 1/β line is intercepted. As the frequency rises, the series impedance of the capacitor diminishes so that at approximately 11 kHz, the load becomes predominately resistive. This technique does not sacrifice any loop gain because the open loop gain (A_OL) and 1/β lines remain stationary. However, the power loss in the resistor can be significant. The usable bandwidth is approximately 3 kHz.

It is worth noting that there is virtually no loss in the peak voltage across the isolation resistor because the current and voltage are out of phase throughout most of the usable bandwidth. Consequently, when the peak voltage is maximum, the applied current is low, minimizing the voltage loss across the isolation resistor. This isolation resistor compensation technique is relatively immune to variations in component values.

Figure 9: Isolation resistor circuitry
(Click on image to enlarge)

Figure 10: Isolation resistor plot
(Click on image to enlarge)

These analysis techniques are generally robust. However, as with any analysis, their usefulness depends upon the assumptions taken. Testing with real hardware, including real cabling and power supplies, can eliminate most assumptions. There are several ways of real world testing which include 'Square Wave Testing' and 'Dynamic Stability Testing'. How to perform these tests is beyond the scope of this article. However, they are discussed in Reference 2.

References
1. The Art of Electronics, Second Edition, Paul Horowitz and Winfield Hill, Cambridge University Press, 1989, p. 242
2. Application Note APEX - AN47, Techniques for Stabilizing Power Op Amplifiers, Section 4, Cirrus Logic, www.cirruslogic.com

Bibliography
1. Network Analysis And Feedback Amplifier Design, H.W. Bode, D. Van Nostrand., 1945
2. Intuitive Operational Amplifiers, Thomas M. Fredericksen, McGraw-Hill Book Co., 1988

About the author
Sam Robinson is Marketing and Applications Manager for the Apex Precision Power™ product family at Cirrus Logic, Inc. His role involves management of product development and marketing, as well as overseeing the applications technical support for this high performance, high precision analog product family. He holds a BSEE from the University of Alabama, Huntsville. Sam has enjoyed a 15+ year tenure working in the power-analog market space.