High-speed, high-resolution analog-to-digital converters (ADCs) have become blazing fast in recent years. It was only in 2006 when a state-of-the-art, 12-bit converter reached 250 megasamples/sec (MSPS). Fast forward to today and the speed has doubled to 500 MSPS. Similar trends are becoming apparent at the 14- and 16-bit resolutions. This suggests that given a bit resolution, the ADC speed is also doubling nearly every two years. As a consequence of the sampling rates, it is becoming increasingly important to close digital timing to ensure data integrity of your end system.

To close timing, locate the setup time (t_su) and hold time (t_h) in both the ADC and digital receiver's datasheets. Setup time is when the data must be valid before the receiver's clock edge, whereas hold time is the amount of time the ADC data must be valid after the clock edge (Reference 1). Adding an ADC's setup and hold time together determines the time data is valid. As a consequence, large setup and hold times is a desired condition for an ADC.

Similarly, for a digital receiver, by adding up the setup and hold time, you get the required data valid time. Here smaller numbers are better. To close timing, the ADC data valid time should always be larger than the receiver's input required data valid time.

Usually, ADC datasheets offer two sets of timing numbers: one for the input clock; the other for an output clock. To understand which set to use for your application, consider how many ADC digital buses are connected to your digital receiver. Regardless of your application, when closing timing, always use values represented in the min column as they represent the worst case.

In the simplest case with one ADC output bus and one digital receiver, the preferred clocking connection to the digital receiver is to use the ADC's clock output, sometimes called dataready (DRY). By following this design practice, you'll maximize the ADC's setup and hold times. Use datasheet numbers referenced to the output clock.

Why? Briefly, we must understand the output buffers internal to the ADC. The ADC's output buffer's timing varies with differences in semiconductor process, buffer-voltage level and temperature. When using the ADC's clock output, variances in process, voltage and temperature apply equally to both the ADC digital and clock outputs. This avoids adding skew between the clock and digital output, maximizing the ADC setup and hold times.

When multiple ADCs are present in a system, consider two distinct scenarios. In the first scenario, consider a situation where all of the multiple ADCs reside on the same IC and provide one clock output per all digital-output buses. (For example, TI integrated two ADCs into one IC in the ADS62P45 design.) Since this is the same IC for all ADC channels, the process, voltage and temperature remain the same throughout. Therefore, for maximum ADC setup and hold times, designers should use the ADC's clock output to latch in the multiple ADC digital buses; provided the receiver can be configured in such a manner. This scenario is similar to the previous case where you can use the setup and hold times referred to as the output clock of the ADC datasheet.

In the other scenario, where you have multiple ADC ICs connected to a single clocked receiver, you must use the ADC timing numbers referred to the clock input. Even if you still use an ADC clock output to latch in multiple ADC ICs outputs, you need to close time using the timing numbers referred to the ADC clock input. At a minimum, semiconductor processes will differ between the ICs, causing greater skew and minimizing ADC setup and hold times. However, if you can close timing using device minimums, you can ensure interface bit errors will not occur as a result of timing.

References
1. "Flip-flop (electronics)", (Wikipedia), click here.
2. For information about other data converters from Texas Instruments, click here.

About the Author

Joe Venable is the systems and applications engineering manager for high-speed data converters at Texas Instruments. Over the past eight years, he has held various positions in applications and systems of analog semiconductors with focus on data converters, medical and broadband communication.
He received his BSEE from Ohio State University, Columbus. Joe has authored several articles and application notes on analog topics, and prepared and delivered several seminars on data converters. If you have a question or comment about this article, you can reach Joe at scb@list.ti.com.

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• "SIGNAL CHAIN BASICS (Part 25): Designing the audio-signal chain for non-audio experts, Part 1", click here
• "SIGNAL CHAIN BASICS (Part 24): Basic networking using the IEEE 802.15.4 PHY/MAC protocol", click here
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• "SIGNAL CHAIN BASICS (Part 18): The op amp as integrator", click here
• "SIGNAL CHAIN BASICS (Part 17): Hysteresis--Understanding more about the analog voltage comparator", click here
• "SIGNAL CHAIN BASICS (Part 16): Understanding the analog voltage comparator", click here
• "SIGNAL CHAIN BASICS (Part 15): Analog/digital converter--dynamic parameters", click here
• "SIGNAL CHAIN BASICS (Part 14): Analog/digital converter--static parameters", click here
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• "SIGNAL CHAIN BASICS (Part 7): Op Amp Performance Specification--Bias Current", click here
• "SIGNAL CHAIN BASICS (Part 6): Op Amp Input Voltage Offset", click here
• "SIGNAL CHAIN BASICS (Part 5): Introduction to the Instrumentation Amplifier", click here
• "SIGNAL CHAIN BASICS (Part 4): Introduction to analog/digital converter (ADC) types", click here
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