PLDs break automotive bottleneck

Due to the rapid adoption of various network protocols throughout the automotive industry, it has become necessary to create a hub to interconnect and consolidate data from these networks and perform processing in a central location. This concept has give rise to the in-vehicle centralized gateway. However, as the complexity of automotive electronics architecture increases, inherently other issues arise that must be looked at by engineering teams to implement gateways effectively. These problems are related to high-speed uploading and routing of software to the various networks; the use of DMAs with the processor and the performance involved; and finally finding devices capable of flexibly dealing with evolving standards and platform scalability versus the fixed functionality devices in use today. First, automotive OEMs have been running into bottlenecks due to the data uploads of hundreds of MB up to several GB of data into vehicles using end-of-production-line programming in order to program software into modules on CAN, MOST, and FlexRay networks. In essence, the industry is seeing the need for the performance of a high-speed router in the vehicle. In order to implement this upload more efficiently, and cut time and costs, there is a movement towards Ethernel—a logical choice for diagnostics; is capable of high-speed data transfer; the hardware is inexpensive; and there is an enormous amount of software applications that are available.

Second, performance must be taken into account. Processor cycles are many times utilized by functions such as data movement and interrupt handling, rather then doing processing, thus impacting throughput and keeping it from running at peak efficiency. By using integrated-hardware DMA controllers, data can be transferred between gateway interfaces and memory or other interfaces in the backgroud—off-loading the processor and allowing it to process more application data. The addition of a coprocessor or auxiliary processor also allows for further system optimization. Transfer sizes and types of DMA transfers must also be considered. Without these avenues of optimization, the design team must account for every single cycle of the processor and minimize data transfer cycles, which does not permit quick changes based on customer requirements.

Finally, finding devices capable of changing as quickly as standards evolve and executing system changes based on OEM platform differences is essential. Current ASSPs are built in fixed hardware, thus making these changes impossible. Many times designers will find ASSPs with an abundance of features and network interfaces, but they may be short of performance—or provide overkill performance-wise and overpriced for the system application. With non-recurring engineering and mask costs almost doubling at every node, and silicon design complexity causing re-spin rates of over 40% as technology moves into 90-nm feature sizes, it is getting too cost prohibitive to spin custom ASICs at every turn. With fixed microcontrollers, there is very little flexibility to change feature sets based on customer platforms, and design cycles can easily take up to two years.

Programmable Logic Devices (PLDs), such as Field Programmable Gate Arrays (FPGAs), offer an alternative to solve these problems. Using these devices, designs can be easily modified to support the evolving nature of networking standards. Flexibility and platform scalability, previously unknown to the automotive industry, are possible thanks to PLDs’ customization to the point of allowing system busses and buffering to be sized to the application and ability to add and subtract functions, interfaces, and feature sets.

Some PLDs also offer embedded hardware processors, soft IP 32-bit microprocessor cores, and Ethernet MAC, along with DMA capabilities to allow maximum performance in a central, or even distributed, gateway architecture. Due to the programmable nature of PLDs, the system designer can even differentiate a product from the competition by including custom logic to augment the available IP cores.

All of these FPGA capabilities can help the automotive engineering community move with more agility in a rapidly changing market, and keep up with the evolution of in-vehicle networking. Recently, with PLD prices being reduced dramatically, the advent of industry standard AEC-Q100 IC stress test qualifications, and having soft IP cores tested and verified at automotive industry-recognized institutions, the barriers to the widespread use of this technology, from development through the full production cycle, have come down. The automotive networking application space can benefit from this revolution.

Kevin Tanaka is automotive marketing and product planning manager for Xilinx