Tech Tutorial: LVDS offers efficient data transmission for automotive applications

Commonly known as LVDS, the standard typically uses a current-mode driver output from a 3.5 mA current source driving a differential line that is terminated by a 100 ohm resistor—generating about 350 mV across the receiver inputs. The 350 mV voltage swing is typically centered on a 1.2V offset voltage.

Because LVDS uses a differential line, magnetic fields radiating from the media are cancelled and little noise is produced (see figure below). Also, using the current-mode driver lowers the risk of ringing or switching spikes. The differential method further enhances LVDS capabilities as the differential receiver rejects common-mode noise from external sources. The excellent noise performance is not only desirable, but it is necessary to maintain and detect the low voltage swing.

The low voltage swing, together with controlled edge rates, allows for high data rates ranging from 100 Mbps to over 1.25 Gbps, per differential pair. The power consumed by the load is small due to the low voltage swing and low current source, 3.5 mA x 350 mV = 1.2 mW. Further advantages can be realized as higher data rates typically result in smaller bus sizes and, in turn, reduced cable and connector sizes.

LVDS is also a prevalent standard, as many semiconductor manufacturers now supply a wide variety of drivers and receivers. Parts are available from National Semiconductor, Texas Instruments, STMicroelectronics, Maxim, and Fairchild. Also, FPGA vendors such as Xilinx and Altera are implementing LVDS I/O into their products. These manufacturers have designed chips useful in a wide variety of applications such as point-to-point data transmission, multidrop or multipoint bus architectures, serialization, deserialization, and data distribution.

Tips for implementation
If LVDS is chosen for implementation, it is important to follow best design practices for a differential transmission line media. First, an engineer should be sure to carefully match impedances throughout the interface. This can be achieved by keeping drivers and receivers as close to the connector as possible; a good rule of thumb is less than 2.5 cm.

Any printed circuit board (PCB) traces should be kept parallel and equidistant; any mismatches in length can cause a phase difference between the voltages, which are manifest as common mode noise. Also for traces, avoid any 90° turns, instead use 45° turns, and radius or bevel traces. If uncontrolled impedance runs are necessary on the PCB, it is recommended that both traces be affected equally and that they run no more than 12 mm in length. It is also good practice to keep differential traces as close together as possible, which minimizes loop area, which will help reduce EMI emissions.

When choosing the PCB itself, it is also recommended that at least 4 PCB board layers are used, one each for: LVDS signals, ground, power, and transistor transistor logic (TTL) signals. Having a solid ground plane will establish a controlled impedance for the transmission line interconnects. Narrow spacing between power and ground will also create an excellent high frequency bypass capacitance. The CMOS/TTL should then be isolated on another layer, separated from the LVDS signals by both power and ground. This will minimize crosstalk interference to the LVDS signal.

Solid ground
Optimizing the design of the power and ground distribution system can also combat unwanted EMI and signal integrity issues. By keeping noise less than 100 mV on the power lines, EMI can be reduced for most devices. If power and ground traces must be used, instead of planes, they should kept wide and low impedance. Employing a short and wide ground return path will create the smallest loop area for the image currents to return. Small loop area will help minimize EMI.

Cables should also employ a ground return wire, connecting the grounds of the two systems. This provides for common-mode currents to return on a short known path and is especially important in box-to-box applications where ground return paths will help limit shifts in ground potential.

It is typically best practice to ensure that one end of the cable is connected to ground via a capacitor or capacitor/resistor network. Use two vias to connect bypass capacitor pads to power and ground to minimize inductance effects. Surface mount capacitors are good as they are compact and can be located close to device pins. Finally, capacitive loading on the transmission line should also be monitored, since an increase in capacitance will decrease impedance, reducing available noise margin.