Clamping circuit tames automotive voltage transients

A load dump is the sudden release of energy resulting from the rapid disconnect of the battery while the alternator is providing charging current to a load. Additionally, jump starting a vehicle can produce an over-voltage condition from the use of series-stacked batteries. Other transients are the result of ignition system noise, relays opening and closing, and one-shot events such as fuses blowing.

Fortunately, the most severe high-energy transients are handled by a central suppressor; typically located near critical (and expensive) components with a high impedance path to the source. The automobile's suppressor must be able to tolerate repetitive load dump peak power dissipations in excess of 1,500W and limit the battery rail excursions to less than ±40V.

Additional protection circuitry is usually required to condition the voltage rail even further. Reverse polarity diodes in series with additional load circuits off the battery rail are effective at blocking negative voltage spikes. The designer's decision to clamp a transient below +40V is dependent on the circuitry receiving the voltage. A DC/DC regulator that receives power from this voltage must be able to tolerate a least +40V in order to prevent overstressing the power components and control circuit. Most modern pulse width modulation (PWM) controllers cannot tolerate voltages in excess of +40V without sacrificing beneficial features, such as synchronous operation, which may be necessary to meet design specification goals.

The use of a current limiting resistor and a clamping zener diode is typically only effective for light load currents, generally below 0.1A, in order to keep the series resistor losses from becoming excessive. The circuit described in the figure below provides a method to clamp the input voltage to a desired maximum voltage, while still retaining a large current delivering capability and minimizing losses during "typical" non-transient operation.

The circuit shown in above has been designed to limit the output voltage to 27V, as set by the zener diode D2. The output voltage is intended to provide power to a DC/DC converter with a 30V absolute max rating. For a steady-state input of 12V, transistor Q2 is in the "off" state and resistor R3 pulls the gate of the p-channel FET Q1 to ground level, turning Q1 on.

Q1 begins to conduct current for input voltages greater than about 3V, and is fully enhanced at 4.5V. The voltage drop across Q1 is quite low and is set by its R_ds-on rating and the output load current. For example, a 3A load results in a voltage drop across Q1 of only 0.16V with an input of 14V. Diode D1 protects FET Q1 from exceeding its maximum gate-source threshold of 20V for high input voltages. For designs that do not have input voltages that exceed 20V, D1 is not necessary.

As the input voltage rises, the output will follow until it reaches the point where zener diode D2 breaks down and conducts current. At this point, the output voltage is clamped to the sum of the voltages across zener D2, R4, and R6. The total voltage across R4 and R6 is only about 0.6V.

Transistor Q3 is configured as an emitter follower, and hence has a current gain of about 1. As collector current flows in Q3, it biases Q2 on which begins to reduce FET Q1's gate-source voltage. The output voltage is held at 27.6V as FET Q1 drops the excess input-to-output voltage across it, acting as a linear regulator. As the input voltage increases, the output cannot increase because additional current flows in zener D2 and forces Q2 to decrease the Q1 gate-to-source drive voltage. This closed loop feedback prevents the output voltage from changing.

System stability
As with any negative feedback closed-loop control system, stability is critical for predictable and reliable operation. The closed loop gain and phase margin determine how well the system responds to external perturbations, such as input voltage changes.

Transistor Q3 is intentionally configured for unity gain as to not introduce excess gain in the feedback path. Transistor Q2 provides a current gain equal to its beta, which can typically be anywhere from 50 to 200. FET Q1 also provides a gain equal to its transconductance multiplied by the output load resistance. This gain is also on the order of 200. The total closed loop DC gain is the product of these two gain terms, which is quite large at greater than 80dB. The load resistance and output capacitance create a pole in the transfer function that rolls the gain of FET Q1 down at a -1 slope or -20 dB/decade above 50 Hz. The output capacitor's equivalent series resistance (ESR) also adds a zero set by the ESR and its capacitance. This flattens out the frequency response beyond 6 kHz. Carefully shaping the frequency response of Q2's gain provides an overall acceptable closed loop frequency response.

A compensation network consisting of R2, C3 and C4 give the necessary frequency shaping. The gain of Q2 decreases at a -1 slope from DC until it reaches a zero introduced from the series combination of R2 and C3. This zero is aligned near the pole near 50 Hz. The parallel combination of R2 and C4 introduces a pole that aligns with the zero at 6 kHz. The total effective loop gain now maintains a -1 slope until unity gain is crossed, as shown below. The example circuit exhibits a bandwidth of at least 70 kHz for load currents greater than 0.5A and a phase margin of 90 degrees over nearly all load conditions. Since there is a low frequency pole set by the load resistance and output capacitance, the bandwidth decreases as the load resistance is increased.