Design Article
Advanced interconnects drive intelligent vision applications: Part 1
Jeff Haight, Sonics Inc.
3/7/2007 1:33 PM EST
MobilEye engineers recognized that their next generation ASIC would require a dramatic increase in features and throughput—and consequently—a totally new architecture to support the required processing power for a universal platform for automotive vision and safety applications. They needed a solution that would enable a dramatic increase in capabilities in order to provide the planned automotive safety and convenience features, as shown below.
To meet these escalating requirements, MobilEye developers recognized that a platform-centric methodology would be required, which would enable the decoupling of IP cores for parallel engineering with data flow design, early architecture exploration of data flows to help characterize processor performance requirements, and the ability to isolate portions of the chip for rapid re-engineering that would reduce derivative product development times and costs. MobilEye engineers chose Sonics SMART Interconnect solutions as the foundation for their platform-centric development methodology.
Background
In complex SoCs, which include a large number of heterogeneous multi-processors (HMPs) and other cores, the interconnect takes on a new level of sophistication in order to enable the optimal performance of each processor. A comprehensive understanding of the interaction and performance of this interconnect is critical for real time performance and vital to the understanding of the overall processing operations.
There are a variety of reasons why new generations of interconnects, and analysis tools to support them, are becoming increasingly critical and important:
1) Growing levels of IC integration, with on-chip heterogeneous multiprocessing, require a clean way to efficiently handle complex data flow architectures with inter-communicating cores, often having a range of new requirements and features, such as different data feeds, operating speeds, types of data endianness, diverse and dynamic levels of security, and quality of service (QoS).
2) Growing awareness that flexible and rapid integration of IP from multiple external sources is key to reducing time to market, with concurrent requirements for integrating the test, verification, and simulation environments.
3) Growing sophistication of the processors dataflow requirements requires the ability to handle multi-processing and multi-threading in efficient, non-blocking manners.
4) Growing appreciation for multi-generation design approaches that efficiently address product upgrades, market segmentation, and product differentiation while maintaining common design infrastructure to keep design efforts manageable
5) Related requirements for clean interfaces to industry standard tools at different layers of abstraction to enable rapid design exploration and optimization through verification and tape out
6) Supporting analysis IP provides a means of tying together pre-silicon and initial physical product verification by providing access and visibility to embedded operations (see Reference 2, below). This analysis is key to in-depth understanding of the operational specifics of the design under different conditions.
7) All of the above factors can be addressed by the adoption of socket-based approaches to minimize the effort of adding or replacing different blocks of IP. OCP (open core protocol) software-enabled architectures have pioneered this concept of socket based design, with other bus architectures adopting many of the same principles in order to provide the needed range of design tradeoffs and performance.
