The total power dissipation in a CMOS circuit can be expressed as the sum of three main components:
(1) Static power dissipation (due to leakage current when the circuit is idle)
(2) Dynamic power dissipation (when the circuit is switching) and
(3) Short-circuit power dissipation during switching of transistors.

Static power dissipation
When a CMOS circuit is in the idle state there is still some static power dissipation. This is the result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic gates have finite reverse leakage and sub-threshold currents. In a silicon chip there are millions of transistor and the overall power dissipation due to leakage current becomes comparable with dynamic power dissipation. Mainly, the values of leakage and sub-threshold currents depend upon processing parameters. Consider an nMOS transistor shown in Figure 1.

Figure 1. Reverse leakage current path due to diode formation

The main leakage current component in nMOS is the reverse-biased diode structure in which the n+ bar forms the n-junction and p-substrate forming the p-junction of the diode. The magnitude of this leakage current is given by equation-1.

(1)

Where Vbias is the voltage across junction,
A is the junction area,
q is the charge of electron,
k is the Boltzmann's constant (1.3807X10e-23 J/K) and
T is the operating temperature.

Diode formation due to MOS structure is inherent, which results in leakage current. This current increases with increases in temperature. Millions of transistors are fabricated on a silicon chip and every transistor constitutes the leakage current. The sum of all leakage currents then becomes significant. CMOS circuits
Another component of leakage current in CMOS circuits is the sub-threshold current, which is due to career diffusion between the source- and drain-region when the transistor is in weak inversion. Sub-threshold current becomes significant when the voltage at gate with respect to source is slightly less or equal to the threshold voltage (Vt) of the MOSFET. At this stage the power dissipation due to sub-threshold leakage current can become comparable to dynamic (or switching) power dissipation. The magnitude of the sub-threshold current also depends upon certain device parameters. The causes of leakage current are complex and far removed from the realm of architecture of digital circuits. Yet the static power dissipation is comparable to dynamic power dissipation.

Out of various techniques to minimize the leakage and sub-threshold currents to minimize static power dissipation one can use variable threshold CMOS (VTCMOS) circuit which is easier to achieve and is discussed here. The basic principle of VTMOS circuit is to keep the substrate separate from source and apply different voltage to it with respect to source (refer the Figure-2).

Figure-2. A variable-threshold CMOS inverter.

Here the substrates of pMOS and nMOS transistors are separated out and having their own voltage source called substrate bias control circuit. The threshold voltage Vt of the MOS device is a function its source-to-substrate voltage Vsb. Normally the substrate of nMOS transistor is connected to GND and the substrate of pMOS transistor is connected to VDD. This ensures the reverse bias condition of source and drain with respect to substrate. There is depletion region around source and drain which inhibits the conduction through substrate. Only the leakage current can flow between source-substrate and drain-substrate. But if the depletion region between source-substrate and drain-substrate is increased the leakage current can be further minimized and this is what the VTCMOS circuit does. During active operation the voltage of nMOS substrate is kept 0V (on GND at which the source is also kept) and the voltage of pMOS substrate is kept at 2V (equal to source voltage). But when the circuit is in standby mode, depicted in Figure-2, the substrate voltages are changed through a substrate bias control circuit. It is 4V for pMOS and -2V for nMOS and hence minimizing the static power dissipation by widening the depletion region and reducing the leakage currents. Drawback of this method is that it requires extra voltage source for substrate biasing and substrate bias control circuitry that increases the chip area. Dynamic power dissipation
Dynamic power dissipation
Dynamic power dissipation occurs when the MOS transistor switches to charge and discharge the output load capacitance at a particular node at operating frequency. Depicted the Figure-3, is a CMOS inverter with output load capacitance CL.

Figure-3 Charging of output load capacitance CL

During charge-up phase, the output node voltage typically makes a full transition from 0 to VDD and an amount of energy from the power supply is dissipated as heat in the conducting pMOS transistor. But during the load capacitance discharge phase no power is drawn from the power supply only the energy stored (during the charge-up phase) in the output capacitance is dissipated as heat in conducting the nMOS transistor. With small static power, the charging and discharging of output node capacitance consumes most of the power in CMOS circuits.

The dynamic power dissipation at a particular output node is then given by:

(2)

Where CL is the total output node capacitance, VDD is the supply voltage at which the output capacitance charges, Fclk is the operating frequency and is the node transition activity factor, which is the effective number of power-consuming voltage transitions experienced per clock cycle. There will be hundreds of output nodes on a chip and will have different load capacitance and different node transition activity factor. Thus, we can write a generalized equation of total average dynamic power dissipation as follows:

(3)

From equation-3 we can easily interpret that by reducing one of the parameters in this equation dynamic power dissipation can be somewhat minimized. Power is always dissipated in CMOS circuit when there is switching at the output node. You can always reduce the power by reducing the operating frequency but due to continuous demand of increasing the speed of data rate in digital systems this method will not give the useful results. α, the node transition activity factor, is a statistical parameter and is data rate dependent and defines the probability of the gate's output to make logic transition during one clock cycle. Only we can predict and can make the rough estimate of its value. The remaining parameters are supply voltage VDD and the output load capacitance CL which are discussed below. Voltage scaling
Voltage scaling
It is obvious from the equation-2 that the power dissipation can be minimized by reducing the supply voltage VDD. Although reduction in supply voltage minimizes the dynamic power dissipation, the trade-off will be an increase in delay. This can be observed by looking at equations 4 and 5 for propagation delay of CMOS inverter:

We consider a metric the energy-delay product. The smaller energy*delay value employs a lower energy solution at the same level of performance- a more energy efficient design as depicted in Figure-4:

Figure 4: Normalized propagation delay and average switching power dissipation of a CMOS inverter, as a function of the power supply voltage VDD

The term voltage scaling used here is different from that of constant filed scaling because we are keeping all other parameters constant instead of scaling them by same factor (like channel length, gate oxide thickness etc). This is the reason that delay increases if we reduce only the supply voltage.

Equations for propagation delay show that the negative effect of reducing the supply voltage upon delay can be overcome by scaling down the threshold voltage accordingly. But reduction in threshold voltage (Vt) of the transistor creates the noise margin and sub-threshold conduction problems. A smaller threshold voltage leads to smaller noise margins for CMOS gates. The sub-threshold conduction current also sets a severe limitation against reducing the threshold voltage. For threshold voltage less then 0.2V, leakage due to sub-threshold conduction in stand-by, that is, when the gate is not switching, it may become a very significant component of overall power consumption.

Load Capacitance (Transistor sizing)
Another way to reduce the dynamic power dissipation is to reduce the load capacitance. Larger load capacitance draws more charge from power supply during each switching and hence increases the dynamic power dissipation. Also the larger capacitance reduces the speed of operation. One can reduce the load capacitance to reduce the dynamic power dissipation. Figure 5 shows the load capacitance and the components at node Vout.

Where Cgd1 and Cgd2 are the overlap capacitance (=2CoW),
Cg1 and Cg2 are the gate capacitance (=CoxWLeff),
Cdb1 and Cdb2 are the drain-source diffusion capacitance, and
Cint is the interconnect capacitance which is due to parallel plate capacitance, fringing capacitance and wire-wire capacitance.

Figure 5 Depicts the load capacitance and the components at node Vout

We have:
Cgate = Cg1 + Cg2
Cdiff = Cdb1 + Cdb2

Total capacitance CL is then
CL = Cgate + Cdiff + Cint

Total capcitance is depicted in Figure 6. By transistor sizing in which you reduce the transistor dimensions like width (W), Channel length (Leff), Oxide capacitance (Cox) the load capacitance can be reduced.

Figure 6. Total Load capacitance CL at the output of inverter

But if we do the same, like increase the oxide thickness to reduce oxide capacitance or decreasing the width of the device, drain to source current will also be reduced at the same threshold voltage and makes the gate slower. We can observe this trade-off in Figure 7 in which the one inverter is driving another inverter repetitively in a chain. Interconnect capacitance can be reduced by keeping the metal wires used to make interconnections between various gates on a chip as small as possible. Keep two metal wires as far as permissible from design rules to reduce the wire-wire capacitance between them. Real circuits are more complex because the gate and wire capacitances are different for different gates, but still, we can make a compromise between various transistors dimensions during their scaling and can reduce the load capacitance up to a certain extent.

Figure-7. Simple inverter chain

Short circuit power
Short circuit power dissipation
From the above discussion, the switching power dissipation is due purely to energy required to charge and discharge the load capacitance and is independent of rise and fall time of the driving waveform. But in a CMOS circuit if the rise and fall time have some finite rise and fall time value, then for a particular time period, during switching, both nMOS and pMOS transistors will conduct simultaneously and provide a direct path between VDD and the ground-rail resulting in short circuit power dissipation. The current component which passes through both the nMOS and pMOS transistor during switching does not contribute to the charging of the capacitance in the circuit, and hence, it is called short circuit current (depicted in Figure 8).

Figure 8: Short circuit current path when both transistors are on

When the input voltage is below threshold voltage Vt, only the pMOS transistor is in the active region and the nMOS transistor is completely off. As the rise time of the waveform attains the value equal to or greater then Vt, the nMOS transistor also starts conducting due to which short circuit current starts flowing between VDD and GND results in short circuit power dissipation.

Pshort = VDD*Ishort

The short circuit current, Ishort, waveform is shown in Figure 9.

Figure 9: Short circuit current waveform

Initially the nMOS transistor conducts in weak inversion region after that in saturation region and finally into the active region. As the rise time of waveform attain the value equal to or greater then (VDD " Vt) the pMOS transistor become turned off completely and inhibits the current flow between VDD and GND. The same phenomena occurs during fall time. The value of short circuit power dissipation can be neglected if the rise and fall time window is very small (a few picoseconds) but is significant if it is noticeably finite in few nanoseconds.

Conclusion
So far we have discussed various techniques to reduce the power dissipation in a CMOS circuit. Good design techniques always require you to make careful trade-offs between the various parameters discussed in this paper.

The total power dissipation comes out to be:

Pt = Pstatic + Pdynamic + Pshort

Energy-delay products can be a good approximation for making various trade-offs like speed, area and design time. It allows a designer to find optimizations that provide the largest reduction in energy for the smallest change in performance. Static or standby power can be reduced by using the VTCMOS arrangement but at the cost of extra bias control circuitry and substrate supply voltage. This is a stringent requirement for laptops, mobile phones and PDAs where these are kept in standby mode for few hours. Voltage scaling can be done to reduce the dynamic power dissipation. While low operating voltage looks very attractive for low-power operation, it is very sensitive to manufacturing variations and operating point change. And if you need to provide margins in your circuit to ensure that it will meet certain speed and power requirements, the advantage of using technologies with very low threshold voltage disappears. Short circuit power mostly depends upon the rise and fall time of the driving signal and comes into the picture only if it is a few nanoseconds.

In order to achieve large potential gains of operating at low voltages, the CMOS circuits need to use some kind of adaptive control on both the threshold voltage and the supply to reduce the effective variations in device parameters. Until energy efficient techniques are developed to accomplish this, the supply and threshold voltage scaling is likely to be modest.

References:
[1] Sung-Mo Kang and Yusuf Leblebici, CMOS digital integrated circuits, Tata McGraw-Hill, 3rd edition-2003.

[2] R. Gonzalez, Benjamin M. Gordon and Mark A. Horowitz, "Supply and Threshold voltage scaling for low power CMOS, IEEE Journal of solid-state circuits Vol-32, No. 8, August 1997.

[3] Y. Taur and T. H. Ning, Fundamentals of modernVLSI Devices. New York: Cambridge Univ. Press, 1998, Ch-2, PP 94-95

[4] Sedra Adel S. and Smith Kenneth C., Microelectronics Circuits, Ch-4, Pg-235-360, Oxford Univ. Press 2004.

About the author:
Vikas Kumar is a Product Validation Engineer at Cadence Design Systems, Inc. Earlier he has been worked as a Signal Integrity Engineer at Logic Eastern. He has a Bachelors of Technology in Electronics and PG diploma in VLSI design. He has also experience in system design work in high speed SONET/SDH boards. He can be reached at vikaskumar1983@rediffmail.com