Design with (low) power while limiting leakage

The total power dissipation in a CMOS circuit can be expressed as the sum of three main components:
(1) Static power dissipation (due to leakage current when the circuit is idle)
(2) Dynamic power dissipation (when the circuit is switching) and
(3) Short-circuit power dissipation during switching of transistors.

Static power dissipation
When a CMOS circuit is in the idle state there is still some static power dissipation. This is the result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic gates have finite reverse leakage and sub-threshold currents. In a silicon chip there are millions of transistor and the overall power dissipation due to leakage current becomes comparable with dynamic power dissipation. Mainly, the values of leakage and sub-threshold currents depend upon processing parameters. Consider an nMOS transistor shown in Figure 1.

Figure 1. Reverse leakage current path due to diode formation

The main leakage current component in nMOS is the reverse-biased diode structure in which the n+ bar forms the n-junction and p-substrate forming the p-junction of the diode. The magnitude of this leakage current is given by equation-1.

(1)

Where Vbias is the voltage across junction,
A is the junction area,
q is the charge of electron,
k is the Boltzmann's constant (1.3807X10e-23 J/K) and
T is the operating temperature.

Diode formation due to MOS structure is inherent, which results in leakage current. This current increases with increases in temperature. Millions of transistors are fabricated on a silicon chip and every transistor constitutes the leakage current. The sum of all leakage currents then becomes significant.