How to power sub-micron CMOS loads with an efficient LDO

In almost every piece of electronics today there is at least one digital IC. Applications such as portable handsets, ultrasound machines, servers and industrial control systems all use digital ICs for processing data. A driving trend in digital ICs such as μP, DSPs, FPGAs and ASICs is Moore's famous law: the number of transistors on an IC doubles about every 2 years. Throughout the decades shrinking geometries (process nodes) from 1000nm (late 1980s) to 600nm to 250nm to 130nm to 90nm to 65nm and now pushing 45nm allows semiconductor manufacturers to fit more transistors in the same area. More transistors means that in the same space you get more features or improved performance, but everything comes with trade-offs.

Issues with powering digital ICs
Shrinking process geometries, more transistors in a chip and higher processing speeds means more power consumption. To combat this power hungry tradeoff digital ICs have lowered their core voltages. The power consumption of a processor is given by the following equation:

P_CONSUMED = cV²f + VI_LEAK

where c is capacitance, V is the core supply voltage, f is frequency and I_LEAKis the leakage current. The first term cV²f is the dynamic power and the second term VI_LEAKis the static power. As processor frequencies increase, lowering the core voltage offsets or lowers the processor's power consumption as shown by the equation above.

Rails, rails, and more rails
Mitigating the increased power consumption issue now requires yet another voltage rail to be supplied in the system. Years ago we had standard 5V and 3.3V rails and because of lower core voltages more and more rails are needed we now see 2.5V, 1.8V, 1.5V, 1.2V and 1V rails. With so many voltages, power supply startup and shutdown become increasingly important. Some digital ICs have requirements or recommendations embedded in the datasheet stating that the power supply must reach a certain value within a specified period, have a monotonic rise and/or track the I/O. If not followed, improper power supply startup and shutdown can lead to latchup and reliability issues.

Another trait of digital ICs is its varying load current requirements. When large amounts of data needs processing the digital IC requires more power as compared to low level tasks or in standby/hibernate mode. When designing a power supply for these processors one specification of importance is the load transient response. Load transient response is how the power supply output voltage reacts to a sudden change in load current. The output voltage transient behavior is often shown as a typical waveform in the datasheet. The smaller the voltage over/undershoot the better.