How to improve FPGA-based ASIC prototyping with SystemVerilog

However, creating an ASIC is a high-investment proposition with development costs approaching $20M for a 90 nm ASIC/SoC design and expected to top $40M for a 45 nm SoC. Thus, increasingly, only a high-volume product can afford an ASIC.

Besides the increase in mask-set cost, total development cost is also increasing due to the reduced probability of getting the design right the first time. As design complexity continues to increase, surveys have shown that only about a third of today's SoC designs are bug-free in first silicon, and nearly half of all respins are reported as being caused by functional logic error(s). As a result, verification managers are now exploring ways to strengthen their functional verification methodologies.

Before starting on a true ASIC design, to demonstrate that concepts are sound and that designs can be implemented, a lower-cost method of using FPGAs to prototype ASIC designs as part of an ASIC verification methodology has been growing in popularity.

Prototyping ASIC designs in FPGAs, while often yielding different performance, often results in the same logical functionality. Further, running a design at speed on an FPGA prototype with real stimulus allows for a far more exhaustive and realistic functional coverage as well as early integration with embedded software. Thus FPGA prototyping can be used effectively to supplement and extend existing functional verification methodologies.

As ASIC designs have grown larger at a much faster pace than FPGA devices, often multiple FPGA devices must be used to prototype a single ASIC. The obstacle of using multiple devices is the task of connecting all of the logical blocks of the ASIC design across multiple FPGA devices. Physically, with the use of the high speed I/O blocks in FPGA devices, connectivity between physical devices has been simplified. However, methods for logically connecting the design blocks have proven to be manually intensive and error prone. With the introduction of SystemVerilog, an evolutionary RTL language, and advanced mixed language synthesis tools such as Mentor Graphics' Precision Synthesis, the procedure for connection has also been simplified.

SystemVerilog
SystemVerilog is not an entirely new RTL language. With its rich set of extensions to the existing Verilog HDL, SystemVerilog is backward compatible with both Verilog 95 and Verilog 2001. Many of these extensions to Verilog make it easier to create accurate, synthesizable models of designs of any size. These extensions also make SystemVerilog easier to use and are truly beneficial to every engineer currently working with Verilog.

The connectivity advantages of SystemVerilog stem from:

1. More compact RTL descriptions with efficient coding methods. 
    
2. Encapsulation, allowing designers to model at more abstract levels with interface descriptions.

Using SystemVerilog for FPGA prototyping does not necessarily mean that the entire ASIC design needs to be written in SystemVerilog to reap the benefits. The obstacle of connectivity can be simplified by just using SystemVerilog to describe the top level module of each FPGA.

Compacting the code
Increased design sizes have increased the number of lines of RTL code required to represent the design. Design bugs can actually be attributed to the number of lines of code written. SystemVerilog results in improved specification of design, more concise expressions and the unification of verification and design. All of which results in earlier time to market and early detection of design bugs. In fact, SystemVerilog can be two to five times more compact than Verilog RTL.

Both VHDL and Verilog have positional and named port connections. Positional ports can be mis-ordered, while named ports can be too verbose and redundant, especially at the top level modules.

SystemVerilog has .name and .* port connections. These methods provide a more concise and less error prone method to describe connectivity. Inherent also in this methodology is a stronger typing on port connections. Port sizes must match, ports cannot be omitted, and all ports must be declared.

Implicit Port Connection features provide designers with very important capabilities, which are not currently available from any other HDL languages. These features provide immediate benefits to both ASIC and FPGA designers, especially in the area of FPGA prototyping. Not only can designers save up to 75% of coding for the top-level instantiation, these features also provide strong, VHDL-like and less error-prone coding styles as illustrated by coding examples.

Comparing a simple, top-level design example:

• With Verilog port interfaces:
  • 250 words / 1,770 characters / 122 lines
  . 
   
• With SystemVerilog .* implicit port interfaces:
  • 72 words / 492 characters / 37 lines

Furthermore, the interesting side-effects of the implicit port connection enhancements include the following:

• Significant reduction in code required to model port connections.
• Stronger VHDL-like typing on port connections.
• Reduction in port-size instantiation errors since all port sizes must match.
• Reduction in omission of ports since all unconnected ports must be listed.
• Less repetitive, time consuming, and error-prone than assembling the top-level design in VHDL or Verilog.

Thus, the top-level instantiation of modules to each other can be much simpler by employing SystemVerilog at the top level of each FPGA device. The lower level blocks do not necessarily have to be converted to SystemVerilog.