How to detect solder joint faults in operating FPGAs in real time

The problem: Solder joint faults in FPGAs
Solder joint faults can be described with a single word – pernicious. Solder joints connect the BGA package, containing an FPGA (Field Programmable Gate Array) core, to the PCB (Printed Circuit Board). Without early detection, electrical anomalies caused by solder joint faults can result in the catastrophic failure of mission-critical equipment.

In order to prevent this, Ridgetop Group designed the Sentinel SJ BIST EPU (Solder Joint Built-In Self-Test Electronic Prognostic Unit). Part of a line of electronic prognostic solutions, SJ BIST provides real-time detection of solder joint faults in any operating FPGA for military, aerospace, and automotive applications.

Solder joint faults can occur with FPGAs found in all types of commercial and defense products. When embedded in BGA (ball grid array) packages, FPGAs become susceptible to failure from solder joint faults. The causes of solder joint faults cannot be isolated, early detection is difficult, and the intermittent failures escalate in severity until devices are rendered unreliable or inoperable. But, as so often seems to be the case, the problem is also the solution...

Stress-related faults
In operational devices, the primary contributors to solder joint faults are thermo-mechanical and shock stresses. Whether from vibration, torque forces, thermal cycling, material expansion, or environmental stresses, the inevitable result is mechanical failure from cumulative damage. At the solder joint level, the damage is seen as a crack at the package/PCB boundary, although there are other possible points of failure in the solder joint network.

Statistical degradation modeling is the current method for predicting solder joint faults in programmed, operating FPGAs. However, since statistics vary and work best at trending large populations, statistical degradation modeling is a stop-gap solution, at best. With SJ BIST, Ridgetop Group provides a true tool for direct, in-situ measurement of prognostic indicators of faults in operating solder joint networks.

Manufacturing-related faults
Since solder joint faults develop during manufacturing as well as in the field, SJ BIST can also be used to detect faults in uninstalled FPGAs. These manufacturing-related faults have their own set of detection challenges. Visual inspection is the current method used for identifying faults in the manufacturing environment. The primary disadvantage is the inability to test and inspect the solder joints.

Visual inspection is limited to the outer row while the board size and other surface-mounted components limit the view even further. As the array density of BGA packages increases, alignment tolerances become tighter. In fine pitch BGAs, there are thousands of solder balls with a 1.0 mm pitch and a 0.60 mm ball diameter. Under these conditions, pad misalignment and insufficient solder become causes of open and partial-open faults.

Even a 100% inspection by X-ray is not guaranteed to find solder joint faults when solder does not wet the entire pad. Another defect, involving the solder ball and paste wicking into a plated through hole, is not readily identifiable even with X-ray imaging. When enough solder wicks into a hole, an open fault is created for that lead.

As an in-situ softcore, SJ BIST is ideally suited for PCB-FPGA reliability testing in manufacturing for harsh environments.

Failure definition
An industry standard defining BGA package failure involving thermal cycles, with or without accompanying physical stresses, is the occurrence of:

1. A high-resistance spike of 300 ohms or higher for a duration period of 200 nanoseconds or longer. 
    
2. Ten or more events that occur within 10% of the time (number of thermal cycles) of the first event.

Types of solder joint failures
Solder Ball Cracks
Over time, solder joints can develop cracks from cumulative stress damage. Cracks typically appear in the package/PCB boundary. A crack can cause the partial separation of the solder ball from either the BGA package or the PCB.

One typical location for a crack is between the BGA package and the solder ball. Another typical location for a crack is between the PCB and the solder ball. Progressive damage to a cracked solder ball leads to another type of failure – the fracture.

Solder Ball Fractures
Once a crack develops, progressive stresses can cause more damage leading to a fracture. A fracture is the complete separation of a solder ball that breaks that point of contact between a BGA and PCB.

As existing fractures remain open for longer periods, contamination or oxidation coats the fracture surfaces. This eventually creates a failure progression from degraded joints to intermittent opens of short duration (nanoseconds) and then relatively long durations (microseconds).

Missing Solder Balls
The progressive mechanical stresses that lead a crack to form a fracture end in displacement. A displaced solder ball not only results in a permanent failure for that pin, the highly conductive ball could be lodged in another location and cause an unwanted short in another circuit.

1. Solder joint failure points (cross-sectional view).
(Click this image to view a larger, more detailed version)

Intermittent Signals
Intermittent signals are caused by solder ball fractures that periodically open and shut. Vibration, motion, thermal, and other stresses cause conditions where a solder ball can move enough to open or shut a fracture. The flexible materials used in PCB fabrication make intermittent signal failures possible. As vibration stress, for example, causes a fracture to open and shut, the circuit of that solder ball unpredictably opens and closes, resulting in an intermittent signal.

The intermittent nature of solder joint failures makes faults hard to diagnose. Also, the input and output buffer circuitry of an I/O port makes it impossible to measure the resistance of a solder point network belonging to a programmed, operational FPGA. Often, a bench-tested assembly passes as No Trouble Found (NTF) because damaged joints make temporary contact.

2. Intermittent failure caused by fractured solder joint and vibrational stress.
(Click this image to view a larger, more detailed version)

Solder Joint No Fault and Fault Tests
The two signal traces illustrated in Fig 3 are for voltages on a 1.0 µF capacitor connected to a group of two I/O ports. The first trace (A) shows the capacitor voltage when one of the two ports connected to the capacitor has a 1 ohm resistor connected in series with the solder joint: the resistance is not high enough to cause a write fault to occur, and SJ BIST correctly did not report a detected fault.

The second trace (B) shows the occurrence of a write fault when the capacitor voltage resistance is increased to 100 ohms.

3. SJ BIST: 1 MHz Capacitor Signal. Top (A) is for a No Fault Condition (1 ohm); Bottom (B) is for a Fault Condition (100 ohms)
[0.5 µs × 2.0V grid].

For clock frequencies of one-half or higher of the maximum clock frequency of the FPGA, the capacitance of the I/O port is sufficient such that no external capacitance needs to be connected, and SJ BIST correctly detected faults with zero false alarms.

Recent analysis of the test data produced and collected by Ridgetop's test lab, as well as the Center for Advanced Vehicle Electronics (CAVE) in Auburn, AL, a major automotive manufacturer's test lab, plus research literature, demonstrate with a 95% confidence level that the first BGA pins to fail are at or near the corners of an FPGA package.