Altium Design Contest winner: yyCAN review

Altium Designer Contest
"Max" Maxfield's announcement of an Altium Innovation Station Design Contest came at a very opportune moment. I desperately wanted to get proficient with this tool. With the 2008 and the 2009 Winter release it has become the 800 pound gorilla of EDA tools: schematic capture, PCB layout, SPICE simulation, signal integrity analysis, microprocessor IDEs (Integrated Development Environment), FPGA support (one might say "FPGAs first and foremost"), VHDL compile and simulation, nice collection of free IP cores, 3D viewing of populated PCB models, C-into-Hardware This is the designer's dream. It doesn't cost a fortune (less than a car, more than a TV). You can order it from DigiKey.

The Design

I wanted a bus controller that was relatively simple. It's getting harder and harder for one individual to do truly unique work. Here is just such an opportunity. Take the best ideas from CAN and create a variation that is simple, hacker friendly and lends itself to implementation on small FPGAs.

Thus various features of CAN were analyzed and re-synthesized. By assuming a shared clock, the bus sampling instant is the same for all listeners. By changing the message format the ID and data fields can be made truly variable length with no upper bound for either the ID or data except for bus responsiveness, which implies a maximum message length. Also the CRC is made optional and part of the data field allowing CRC implementation either in the yyCAN controller or in the host processor.

Most of the flavor of CAN is retained.

Download James Brakefield's article.