How to Choose the Right FPGA

Field Programmable Gate Arrays (FPGAs) are a tremendously exciting implementation platform. They are used to replace Application Specific ICs (ASICs), such as digital receivers, and programmable general purpose processors or DSPs.

Even though programmable logic has been around for many years, the latest generation FPGAs are more powerful and are making their way as the right solution for many embedded applications.

Each new generation of FPGA devices delivers faster speeds, improved density, larger memory resources and more flexible interfaces.

Embedded system board vendors face a difficult challenge, since each customer has a different mission unknown to the board designer at the time FPGA component selection is made. Successful new product definition requires an intimate knowledge of available device features, insights into market space application trends, and an appreciation for how FPGA resources map into those applications.

This article highlights the latest family of Xilinx FPGAs and analyzes their specific features and tradeoffs to aid engineers in selecting the most appropriate FPGA for their application needs. Comparisons of the most recent Xilinx products are provided with regards to performance, power consumption, signal integrity, serial fabrics, memory, and speed.

The Xilinx Virtex-4 Family
To illustrate the range of FPGA resources available in current offerings, we will look at the Xilinx Virtex-4 family. Unlike the predecessor Virtex-II Pro family, Xilinx has split the seventeen Virtex-4 product offerings into three device groups, each targeting different requirements. Before we look at how these groups are defined, we will briefly discuss the major types of Virtex-4 resources and functions.

Logic resources are arranged in "slices" consisting of a look-up-table (LUT), multiplexers, a Boolean logic block, and an adder/subtractor with carry functions. Four slices make up a configurable logic block (CLB), the basic element used for creating state machines, combinatorial logic, controllers, and sequential circuits.

Memory has become much more flexible in the latest generation FPGAs and comes in different forms. Distributed memory is used for LUTs, FIFOs, single- and dual-port RAMs, and shift registers. For larger memory structures, 18 kbit block RAMs can be used for deep FIFOs, large circular delay memory buffers, deep caches, as well as bigger single- and dual-port RAMs.

Xtreme DSP
One of the more significant advances in the Virtex-4 family is the new "XtremeDSP" slice. Following the market demand for more powerful signal processing structures, Xilinx has surrounded the popular 18x18 hardware multipliers first introduced in the Virtex-II series with a 48-bit adder/subtractor capable of acting as a registered accumulator. Due to tight, dedicated logic, this facility can operate at clock speeds up to 500 MHz and can propagate the results between DSP slices at the same rate with 48-bit precision.

The 48-bit path allows this fast, fixed-point hardware to rival the precision of floating-point engines by preserving the 36-bit multiplier outputs with plenty of overhead for bit growth as results propagate through cascaded slices.

Each DSP slice features 40 dynamically controlled logical and arithmetic modes and supports mode changes during runtime without the need to recompile the FPGA. This way, each XtremeDSP slice behaves like a miniature DSP processor; there are as many as 512 of these in a single FPGA!

XCITE Active Termination
Connections to a diverse range of external hardware devices are well accommodated with 20 different user-configurable interface standards for the device I/O pins. New in the Virtex-4 is the XCITE active termination feature: it not only provides programmable termination within the FPGA to drastically reduce the number of external discrete resistors; it also dynamically adjusts termination impedance to track changes in drive levels due to process, temperature and device variations.

Source-synchronous interfaces include serializer/deserializer blocks that match faster data rates up to 1 GHz on external data buses to slower, wider buses inside the FPGA to help reduce power. Interfaces to many fast external memory devices, including DDR and QDR, are made easier with programmable clock and data skew circuitry to match complex setup and hold time requirements.

Clock Management
Digital clock managers allow different regions of the FPGA to be operated at different clock frequencies that can be synchronized from various external clock references. Frequency synthesizers with multipliers and phased-matched clock dividers precisely align external timing signals with data sources and destinations.