Selecting memory controllers for DSP systems

DSP systems often include multiple embedded processors and hardware accelerators. The performance of these systems is typically limited by factors such as I/O bandwidth, memory distribution, and memory speed. This is particularly true when the system components share a memory interface. For such systems, it is critical to choose the right memory controller.

Different memory controllers offer latency distributions that make them suitable for specific applications. For example, a slot-based controller with fixed priorities can offer deterministic latencies, while buses such as PCI-Express and CoreConnect offer lower latency at peak loading but higher average latency.

It is extremely difficult to predict the performance of the memory system and the effect of contention without a solid model of the system. It is therefore important to invest in modeling before beginning development. This modeling should include allocating of threads/tasks to resources, identifying any custom hardware needs, and determining the size and speed of the I/O. The modeling can performed using a number of methods, including "back of the napkin" calculations, spreadsheet analysis, or by building a physical prototype.

In this article, we examine a unique "virtual prototyping" approach to modeling. We use this approach to model a MPEG II application in a Xilinx FPGA. We evaluate two memory access schemes for this application: the MPMC Memory Controller from Xilinx, and the CoreConnect Bus specification for FPGAs.

Virtual Prototyping
The virtual prototyping approach discussed in the article is based on the VisualSim solution from Mirabilis Design. VisualSim is a graphical platform for analyzing the performance of hardware and software systems. It is based on a library of parameterized components including processors, memory controllers, DMA, buses, switches and I/Os. Using this library of building blocks, a designer can construct a specification-level model of a system containing multiple processors, memories, sensors and buses. Model construction is a process of connecting icons that represent the IP in a graphical editor, as illustrated in Figure 1.

Simulations can be explored by varying parameters for the input scenarios, data rates, priorities, speed, or size. By analyzing the simulation results, the designer can choose the solution that achieves the required latency with the lowest power, smallest fabric configuration, and highest system throughput.

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Figure 1. VisualSim model of the Xilinx Virtex 4 FX Platform: e405 with MPMC Memory Controller.

Project Overview
This project evaluates the performance of a MPEG II algorithm implemented in C. The target system is a Virtex-4 FX with up to two hardwired PowerPC e405 cores connected to DDR2 SDRAM. We evaluate two memory access schemes for this application: The Multi-Port Multi-Channel (MPMC) Memory Controller and the CoreConnect Bus.

The MPMC Memory Controller (Figure 1) is a popular option for this type of application, as it provides an extremely efficient means of interfacing the processor and key high speed devices to SDRAM. The CoreConnect Bus (Figure 2) is another popular option. It supports multiple masters, including the PowerPC caches and key high speed devices, connected via a slave port to the SDRAM. The preferred technique depends on which approach will provide the best performance in terms of throughput, latency, and processor efficiency.

To investigate the similarities and differences between the two approaches, we constructed models of both configurations using VisualSim graphical modeling environment. The exploration models did not require any software coding. The designer only needs to connect the different modeling elements, create the right traffic mix from the processor and high speed devices, and select parameter settings that match the anticipated design.

For more details on the MPMC Memory Controller, download the datasheet from http://direct.xilinx.com/bvdocs/appnotes/xapp535.pdf. Details on the CoreConnect Bus can be downloaded from http://www.xilinx.com/ipcenter/processor_central/coreconnect/coreconnect.htm.

(Click to enlarge)
Figure 2. VisualSim model of the Xilinx Virtex 4 FX Platform: e405 with CoreConnect Bus Model.