Timing-driven Simulink FPGA synthesis

Until now, the creation of an optimized HDL netlist has been a largely manual process, usually done by a different person than the algorithm designer. This hardware designer must make sure that the design meets timing requirements, is time division multiplexed (TDM) to maximally utilize resources, and has the control plane logic necessary to move data in and out of the data path.

What is needed is a tool that understands both the underlying FPGA architecture and the top-level system constraints. A tool that can automatically implement pipelining, register insertion , time-division multiplexing of scarce MAC resources, and other optimizations necessary for truly optimized HDL.. Such a tool would enable designers to make system-level modifications by editing high-level constraints, and synthesize optimized HDL with the click of a button.

The second generation of system design tools developed by FPGA vendors are beginning to incorporate such functionality. The remainder of this article illustrates the design productivity advantages of using such tools. As an example, we use a multi-channel, complex filter with changing design specs. This example can be extended to other applications such as FFTs, digital up and down conversion, and other common processing-intensive DSP applications.

Building a multi-channel, complex FIR filter using Simulink
A FIR filter is the workhorse of many DSP designs. We use it here to explore the productivity benefits afforded by the next generation of Simulink synthesis tools. Figure 1 illustrates a FIR filter in the DSP Builder advanced blockset library.

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Figure 1. Building a FIR Filter using DSP Builder advanced blockset library.

To build a filter, the designer, the designer drags the filter block from the blockset library. The filter parameters are set in the filter GUI. Within Simulink, it is easy to add virtual sources, like sine wave sources, modulated sources, or even noise-like signal. Output signals can be terminated with virtual oscilloscopes and spectrum analyzers to view both time and frequency domain responses. In this example, the circuits surrounding the filter block are sinusoidal signal generation blocks, along with virtual oscilloscopes to view in input and output.

Generally, the first step in the design process is to simulate the frequency response within Simulink, as illustrated in Figure 2. After Simulink simulation, the design is ready to be implemented in hardware.

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Figure 2. Simulating the frequency response of a filter within Simulink.

This is where the Simulink synthesis tools provided by FPGA vendors come into play. These tools take the Simulink representation of the design and convert that description to either HDL or a programming bit-stream for a particular FPGA.

This design flow is well understood and accepted by the DSP design community. However, it does not allow the designer to set system level constraints such as clock speed, number of filter channels, etc. at the Simulink level. Also missing has been the ability to automatically TDM the requested number of channels, insert pipeline registers to meet clock rate requirements, and incorporate control plane logic. This is still largely a manual process.