Designers slept well when using a process qualified for production, knowing that as long as their designs obeyed the rules, good yields would result.

With today's sub-100nm process technologies, the fab too often discovers that parametric and systematic yield issues creep into volume production. We contend that lower yields, due to systematic and parametric failures, are no longer just the fab's problem. These failures often occur because complex topologies, created by designers, were not envisioned or adequately characterized during process development.

The fab is attempting to address such yield fallout through more complex design rules and guidelines that will hopefully capture the variety of clever layout choices designers may make. But the effective application of more complex rules and guidelines requires more sophisticated analysis tools not yet available. Lacking such tools, the fab may opt to mitigate the emergence of new yield limiting mechanisms by imposing greater restrictions on the choices that designers can make (e.g. by allowing only one poly gate orientation, or by forbidding certain via cluster configurations). Such restrictions may create area penalties that dilute the benefits of adopting the new process technology.

A framework that allows manufacturers and designers to work together in a collaborative fashion is critically needed to address these new process-design interactions. Such a framework must first supply characterization solutions for obtaining the data necessary for both process and design yield improvement. This paper describes a solution to this challenge.

Practical and effective parametric characterization
Achieving practical and effective parametric process characterization in the sub-100nm domain poses a number of challenges, not the least of which are:

1. A critical need for a greater density of test structures on the test mask which support fine analog measurement resolution.
2. Measurement of device parametric variability within-die (not just die-to-die, wafer-to-wafer, and lot-to-lot).
3. Measurement of device parametric variability over a greater number of device contexts and topologies.
4. Lower test time per test structure
5. A characterization solution extensible across the process life cycle.

The parametric ActiveMatrix approach
The term Parametric ActiveMatrix ("PAM") is coined to refer to a circuit, similar to a memory array in that it employs an addressable, cell-based architecture, but innovative in that it enables high resolution analog measurements not possible with memory arrays. Each PAM cell contains any one of a wide variety of test structure types and sizes (Fig. 2). Many of the same discrete test structures utilized in conventional testchips can be incorporated into the PAM platform. Thus, this architecture combines the density improvement of cellular arrays with the measurement resolution obtainable with discrete test structures.

With the PAM, sets of test devices are conveniently designed and grouped to fulfill learning objectives such as design rule optimization, device IV characterization, device mismatch characterization, OPC model verification, etc. Conventional test structure elements (sometimes referred to as 'test element groups,' or TEGs) require far greater silicon area to achieve similar sets of experiments. The sections below describe how the Parametric ActiveMatrix approach meets the aforementioned challenges to effective parametric process characterization.

Greater parametric test structure density
Discrete test structures consume large amounts of silicon area, primarily due to the large pads needed to individually probe these structures (Fig. 3). The geometric increase in the number of design rules and (hence) test structures required with each new technology generation has made it prohibitively expensive to continue this conventional approach. In addition, a larger set of parameters must be monitored as the process goes into production.

This creates a difficult problem since the available scribeline space does not increase with each process technology generation. In fact, it has been steadily reduced as scribeline widths have shrunk from 100um to 80um and today even to 50um. In both technology development and production scribelines, the PAM platform reduces test structure area requirements dramatically, providing a much-needed solution.

As an example, considering a square pad size of 70um on a 130um pitch, 1000 parametric test structures would consume approximately 35 mm² of area using conventional methods. With the PAM platform, a single pad frame consisting of about 20 pads can accommodate over 1000 devices for full analog test and consume only about 4.3 mm² of area. Often, smaller cell sizes can be used to further reduce area.

The PAM supports a full Kelvin (force/sense) measurement on each terminal of the test device within a cell. Consequently, the analog measurement resolution is compatible with that of the most accurate discrete test structures. In fact, the only types of tests done with discrete structures that are not supported by the PAM are those requiring significant current or voltage overstress, or applied voltages below wafer ground.

Careful design techniques need to be employed to ensure that the leakage floor of the PAM platform is suitably low, and that the circuit is robust against wide excursions of process parameters commonly encountered in the early stages of process development. Circuit parasitics of the array that may impact measurement accuracy must also be properly handled.

Figure 4 summarizes the area efficiency and measurement resolution of discrete test structures, SRAM/ROM's and the active matrix platform technology for comparison. SRAM and ROM types of memory arrays offer the lowest area per test device. Though these circuits typically provide only a pass or fail (i.e. binary) signature, the fab is able to use them to quantify the probability of functional failures occurring due to random and systematic defects down to part-per-million levels. The PAM fills the increasingly important need for obtaining statistics of analog quantities within-die.

Characterization of Within-Die Parametric Variability
Two identical devices within the same circuit behave differently due to random fluctuations in their dimensions (e.g. due to varying etch bias, or edge roughness) and composition (e.g. due to dopant variations), a fact well appreciated by analog designers since the beginning of integrated circuit design. Today, this intrinsic variability has become a dominant concern for all circuit designers. At sub-100nm geometries, within-die variability is emerging as a critical cause of yield fallout for digital designs, not to mention analog. It is a purely physical effect that cannot be eliminated. Variations in transistor properties die-to-die, wafer-to-wafer, and lot-to-lot indicate processing shifts related to uniformity across the wafer, the lot, or in time. The advent of 'fast' and 'slow' corner models signified that designers could no longer ignore these variations. With sub-100nm process technologies, variations in threshold voltage, drive current, off-state current (just to name a few parameters) are becoming significant across the die itself. Design flows are faced with incorporating true statistical approaches to account for them. Within-die parametric variability must be accurately measured if the process yield ramp & design process is to accurately account for it.

The Parametric ActiveMatrix platform provides the means to gather the data necessary to create statistical models of parametric variability. The same area savings that affords more design rule experiments and device topology variations also allows sample sets of hundreds or even thousands of identical devices from which true within-die statistics are measured. The need to characterize and model intrinsic variability in a production-worthy process will intensify, and will represent a new imperative for improving yield in 65nm process technologies and below.

Reduced test time
With the enormous increase in the number test devices for process development and parametric yield ramp comes an enormous increase in test time. The current PAM platform approach does not solve the problem of increased total test time. However, it does alleviate the issue by reducing the per device test time. By testing thousands of devices with one probe touchdown, probe head movement is reduced by about a factor of 100. Thus the test time associated with probe head movement is largely eliminated. Further innovation in parallel test and other techniques are still needed, however, to prevent test time from becoming a severe bottleneck for statistical process characterization.

Platform flexibility and process life cycle support
In order for it to be a true platform, the architecture must scale with the standard padframe used by the fab for probing the test vehicle. The padframe footprint is typically fixed so that a single probecard is used. It is essential that the PAM platform allow the array to adapt to the dimensions of the common padframe. For example, if the pad frame consists of total 20 pads in a single or dual row in the X-axis, then the PAM implementation must have a fixed dimension in the X axis, but can grow arbitrarily in the Y direction. Such scalability is key to accommodating different numbers and sizes of test cells.

The PAM approach provides a flexible cell size within the architecture. This is important since there is a need to accommodate a wide variety of devices and topologies. Some devices can be small and some can be large or complex. For example, when characterizing threshold voltage variability, the devices tested will include both isolated and dense transistors. The footprint of an isolated transistor will be much smaller than the footprint of a dense transistor array.

The PAM approach allows utilization of the same platform architecture across all phases of process life cycle. It is preferable to use the same platform architecture that was used for characterization during development and pilot stages during production also. The PAM platform affords the same high test structure density in the scribe lane as it does in the full reticle (though the scribe array sizes are obviously much smaller). The higher density allows product engineers to effectively monitor a larger set of devices and parameters during production than conventional scribe modules allow. Since common circuitry is used in each PAM form factor, differences in test structure characteristics observed in moving from one development phase to another reflect true process changes and not changes in the test structure design or test protocol.

Parametric process characterization methodology
Foundries have made a significant investment in their yield ramp and process characterization infrastructure. Any new characterization technology must allow a fab to leverage this existing investment. The PAM platform approach utilizes the fab's existing parametric test hardware and parametric test probecard. No hardware changes of any kind are needed.

From an overall methodology standpoint, the fab can include the PAM circuit alongside other test structures on its test reticle (or include it in the scribe), manufacture the test reticle, probe it, measure electrical parameters using existing parametric testers and feed the measured data into their existing yield management system(Fig. 5). Analysis methods can be built depending on the yield learning/ramp objective.

This methodology fits in well with the fab's current methodology while enabling advanced parametric variability characterization.

Effective parametric yield ramp, an imperative
Parametric variability has always existed in the IC manufacturing process. However, its increasing impact on yield cannot be ignored without long term damage to the industry's health. Both manufacturers and designers must work collaboratively towards reducing and managing the impact of parametric variability.

Employing a silicon-proven Parametric ActiveMatrix platform methodology delivers the following benefits to the manufacturer:

• Reduced silicon area consumption and overall mask cost by virtue of its addressable array architecture. An order of magnitude increase in test structure density may reduce the number of test mask sets over the process development lifecycle.
• Practical means to gather within-die statistics of parametric variability.
• Economical means to test many device topologies relevant for yield improvement.

• Access many more parameters to aid in diagnosing product yield.
• Include tests of design topologies representative of product features.
• Obtain parametric statistics for correlation with product yield.

A PAM platform methodology can foster a collaborative environment between design and manufacturing, a condition key to driving parametric yields higher.

About the authors
Prashant Maniar is co-founder and chief strategy officer of Stratosphere Solutions Inc., and has spent the past 10 years within EDA focusing on design for test (DFT), design for manufacturability (DFM) and Design for Yield (DFY). Dr. Maniar received his M.B.A from Santa Clara University, his M.E. from the University of South Carolina and his B.E. from University of Bombay, India. He is also an active member of the TiE (The Indus Entrepreneurs) Semiconductor special interest group. You can reach him at: Prashant Maniar. Dr. Jim Bordelon is co-founder and chief technology officer of Stratosphere Solutions Inc. Previously, he was managing director of the TestChip Division of HPL Technologies, now part of Synopsys Inc. Dr. Bordelon has a Ph.D. from the University of Texas at Austin with a focus on hot carrier effects and high-field transport of silicon devices. He holds a Master of Science degree in electrical engineering from the University of Texas at Austin and a Bachelor of Science degree in electrical engineering from The Georgia Institute of Technology. He can be reached at: Jim Bordelon.