Limitations Of Traditional At-Speed Testing

The most important trend in scan test over the past five years has been the mainstream adoption of testing for at-speed defects, sometimes called AC scan. Simply put, at-speed defects are manufacturing-induced contaminations or out-of-spec variations that cause a circuit to fail when run at speed, but the circuit will operate correctly when run at some slower frequency.

The most common fault model used by ATPG tools to target these types of defects has been the transition fault model. The transition fault model is a straightforward extension of the stuck-at fault model, whereby the conditions for detection are that a transition has occurred on the node, and the logic effect of that transition has been propagated to and captured by a scan able register. Note that detection of a transition fault is independent of which path is used to sensitize and propagate the fault. Thus testing a transition fault along a short path is considered equally good as testing that same fault along the longest path. But a longer path will have a smaller slack, and will be more sensitive to the additional delay caused by an at-speed defect. Specifically, a small delay defect could be missed if a shorter path is used. This situation is exacerbated by the behavior of commercial ATPG tools, which have been optimized for run time performance. The most likely tests tend to use shorter paths instead of longer ones, since tests using shorter paths tend to have an easier and quicker solution.

While transition tests require some additional computation to generate, the total number of transition faults is a linear function of circuit size and the same number as stuck-at faults. Thus it remains feasible to generate high-coverage transition tests for an entire large design, even designs with hundreds of millions of gates. Transition tests can be applied through existing scan-based DFT structures, and only rely on a pair of at-speed clock pulses either from the tester or from an on-chip clock generator such as a PLL. The cost to adopt this methodology has been primarily limited to the additional test patterns required to achieve high transition fault coverage.

The other at-speed fault model currently in use is the path delay fault model. This model tests the cumulative effect of all delays along a specific path. Unfortunately, the number of paths as a function of circuit size can grow exponentially, and it is therefore only practical to target a limited number of critical paths with this fault model. It should be noted that applying path delay tests uses the same methodology as transition faults, and the cost here is likewise a function of the additional patterns to test these faults.

Even if both of these fault models can be targeted, a significant testing hole remains: small delay defects on untested critical paths and on non-critical paths. The transition fault model covers all the nodes in a design, but will only detect defects that introduce a large delay. The path delay fault model will detect small delay defects along a tested path, but only a very small fraction of the paths in the design can be targeted.

Small Delay Defects and Increasing DPPM

Experimental data over the past 15 years has shown that the failure distribution due to delay defects is skewed towards smaller delays. Of particular note is that this data consistently indicates that the majority of devices that fail due to delay-related defects fail due to delay defects smaller than the typical clock cycle times for the respective technology node. Figure 1 shows an example published by IBM for a 450nm technology [1]. This particular device had an operating frequency of 50MHz, or 20ns.

As design sizes and performance increase, more and more circuit nodes will be susceptible to a small delay defect. However, competitive pressures in the electronics industry demand the delivery of higher and higher quality parts. Today, applications from automotive to consumer often require near-zero defect rates from their suppliers. If such delay defects are not being detected by at-speed scan tests, either extensive at-speed functional testing on the wafer will need to be added, or the packaged part will also need to be tested in a real system environment, both of which are very expensive options for high- volume markets.

The initial approach considered for testing small delay defects was to perform greater than at-speed test. This approach "overclocks" the design and then masks out any scan able registers that receive paths longer than the aggressive clock cycle being applied. By applying these tests in discreet increments of reduced cycle time, one can test long paths at the functional cycle time, and the shorter paths at some fraction of the functional cycle time. Thus far there has been little adoption of this approach because it suffers from at least two highly undesirable side effects. First, the on-chip clock generation circuitry and clock distribution networks must be designed for frequencies well above the functional design " in some cases 2X faster or more. This additional design overhead is difficult and expensive at best, and impossible at worst. Second, this approach will also detect redundant delay defects, and failures from these will lead to unnecessary yield loss. Specifically what are redundant delay defects? These are additional delays that do not cause the part to fail in any real application. For example, if the functional cycle time is 10ns, and the longest path through a particular node is 7ns, the design can tolerate up to 3ns of additional delay on that node. However, if the design is tested with an 8ns cycle time, only a 1ns delay can be tolerated and, for example, a 2ns delay would cause the test fail, even though the part would otherwise operate correctly.

A New Approach to Target Small Delay Defects

Due to the serious limitations concerning the greater than at-speed testing approach, and considering that new test methodologies are rarely accepted unless they have minimal impact on the design and the design flow, Synopsys has developed a new technology to target small delay defects. To maximize ease-of-adoption this technology is based on the TetraMAX ATPG and TetraMAX DSMTest products. Our approach preserves what is already good about today's transition testing: no additional design impact, a predictable flow, and scalable performance. This technology uses the existing transition fault model and enhances ATPG by changing test generation to target a transition fault along its longest path rather than its easiest path, and by modifying fault simulation to calculate the delay of each path along which a transition fault is tested. This approach is evolutionary from the designer's and test engineer's perspective, but revolutionary from the way ATPG tools have traditionally operated.

Let's consider the very simple example of a 4-bit ripple-carry adder shown in Figure 2. The slowest path through that circuit is typically the LSB input to the carry output. Traditional ATPG would nominally test a transition fault on the LSB input by propagating it to the LSB sum output, typically a short path. In our approach, ATPG will instead first attempt to propagate the transition fault on the LSB to the carry output, which is the longest path. As in traditional ATPG, fault simulation will give credit anytime a fault is detected, but now will also measure the "goodness" of the path or paths that were used to detect a transition fault relative to the longest path through that fault. By allowing fault simulation to consider fortuitous detections occurring along long paths, ATPG only needs to focus on those faults that need explicit test generation to test transition faults along the longest paths.

If ATPG cannot find a test for a transition fault along its longest path, the test generator will try other long paths before aborting that fault. Thus this "relaxation" approach means that coverage does not significantly degrade even if they are many untestable paths in the design. The user may also enter several parameters that tell ATPG the largest size delay defect to target with this approach, and how close ATPG needs to come to the longest path for a "good" test.
The Critical Link: Accurate Timing Analysis
The Critical Link: Accurate Timing Analysis

Synopsys' new approach means that the ATPG process is now timing-driven. Specifically, test generation makes decisions using timing information, and fault simulation grades tests using this same timing information. This is not just a matter of ensuring that each path meets a required delay and that test patterns will work on the tester. Each test generation decision can only be made correctly if the timing model accurately matches the behavior of real silicon. However, ATPG must also consider the run-time performance. Test generation may make thousands of decisions per test, and there may be thousands of tests, so it is not feasible to perform a dynamic timing analysis every time ATPG needs to make a decision.

Synopsys' PrimeTime static timing analysis provides what is needed. Its slack directly specifies the sensitivity of each node to a delay defect. And the relative goodness of each test generation decision can be easily calculated from the differences between slacks on each node in the decision space. Just as important, PrimeTime is the industry's de-facto sign-off timing analysis tool, and it fully models all key process, physical, noise and clock network effects [2] required for accurate timing analysis of nanometer designs. Attempting to build another timing analysis engine within the ATPG tool would inevitably lead to results that are less accurate than what PrimeTime already provides.

Figure 3 shows one possible flow to generate slack data from PrimeTime, to then grade traditional transition test patterns for small delay defect coverage, and finally to generate additional patterns that will test small delay defects missed by the original transition patterns.

New Metrics To Measure Test Quality

A remaining challenge for small-delay defect testing is a useful and concise way to report the quality of tests targeting small delay defects, traditional transition fault patterns and other at-speed tests [3] [4]. Any new metric should consider the industry acceptance of stuck-at and transition fault coverage, and thus should have the following properties:

• General " regardless of the original target fault model, any test pattern set should be measurable.
• Comparable " it should be easy to determine the relative goodness of two or more pattern sets.
• Predictable " the metrics should correlate with DPPM rates in production testing.

Since small delay defect testing can be considered an enhancement to transition fault testing, one proposal was to just enhance transition fault coverage to consider coverage of small delay defects. This approach has been rejected because it would be ambiguous whether a transition coverage number refers to the traditional transition fault model or the new small-delay defect model.

Instead, we have introduced a new metric called delay effectiveness. This metric complements the existing transition fault coverage metric by measuring how well an at-speed pattern set covers a range of delay defect sizes on each testable transition fault. This metric specifically excludes coverage of redundant delay defects, because these do not cause the test or the real application to fail, as explained earlier. Like the stuck-at and transition fault coverage metrics, delay effectiveness is typically reported as a percentage between 0% and 100%, where a result of 100% means that every testable transition fault was tested through its longest path.

Conclusion

We have presented a new technology to reduce DPPM by testing for small delay defects. The solution presented is based on the existing transition fault model, new ATPG algorithms, new flows for timing-driven ATPG, and new metrics to measure test effectiveness in detecting small delay defects. Using this technology, DFT and test engineers will be able to generate small-delay defect test patterns on very large designs with reasonable performance and cost, and with no design or DFT changes, additional tester requirements, or loss in yield.

References

[1] P. Nigh and A. Gattiker, "Test Method Evaluation Experiments & Data," International Test Conference, Oct. 2000.
[2] J. Zejda and P. Frain, "General Framework for Removal of Clock Network Pessimism," ICCAD, 2002.
[3] E.S. Park, M.R. Mercer and T.W. Williams, "Statistical Delay Fault Coverage and Defect Level for Delay Faults," International Test Conference, 1988.
[4] Y. Sato, S. Hamada, T. Maeda, A. Takatori, and S. Kajihara, "Evaluation of the Statistical Delay Quality Model," Asian and South Pacific Design Automation Conference, 2005.

About the aauthors:
Cy Hay is TetraMAX product manager at Synopsys, Inc
. He can be reached at: chay@synopsys.com
Rohit Kapur is an IEEE Fellow and a Synopsys Scientist. His email address is: :rkapur@synopsys.com