Ensuring Power Designing Works at 65nm

To accommodate foundry customers' 65nm designs, it is in everyone's best interest to fully leverage TSMC processes with compatible, power-saving EDA tools. TSMC already brings to bear low-power methodologies and IP aimed at reducing dynamic, active, and standby power leakage. All of these low-power methodologies require fully automated EDA support.

However, a fully optimized low power methodology requires more than just process support. It also requires that design tools in the methodology communicate low power design intent in a single, standard format. The Si2 Common Power Format (CPF), the first low-power EDA format embraced by TSMC for 65-nm low power design, enables this capability.

Ultimately, low power designs employ a variety of power reduction techniques such as power gating, multiple-voltage domains and dynamic voltage scaling. Because there are so many concurrent variables in designing with multiple techniques, TSMC has taken a phased approach to ensuring that automation of these techniques results in verifiable improvements to 65nm designs. This article describes an early program to validate the Common Power Format for use with TSMC technology.

The project

The objectives included:

• Validating the design technique in silicon, using CPF-based EDA tools
• Verifying functionality and timing results for the technique, as well as improving verification technologies
• Enhancing communications between logic design and physical design teams
• Looking for opportunities for further automation
• Achieving synergy between TSMC low-power IP and EDA tools for implementing power-gating and power shut-down circuitry.

In any design project, design intent must be clearly specified so everyone is on the same page. CPF automates this task by providing a single file with standard definitions of power intent. This allows designers and design tools to draw from a common data set all along the design flow. Once in place, this capability quickly makes it apparent that there might be more opportunities for driving CPF awareness into a low power methodology. To verify this, the project had to clearly spell out what techniques would be used (Figure 1).

1. The Boxed Area Defines TSMC's Low-Power Test Run.

The baseline for the project was a comparison to previous design techniques, without CPF support. The hypothesis that there would be dramatic improvement was safe; the impact of earlier power-reduction design techniques (e.g. area optimization and clock gating) on functionality and timing was minimal, but so was the reduction in power. The advanced techniques now being applied, such as power gating, were also expected to impact functional and timing verification, so it was important to gauge that impact and work to minimize it to preserve high levels of validity.

The "proof" design
TSMC used a large block similar to advanced system-on-chip designs. It involved over 100,000 instances, 50 (RAM) blocks, and over 100,000 nets.

In the design flow, we used CPF-enabled EDA tools, but we purposefully minimized the power-aware design techniques to a single subset: power-gating. This allowed us to better evaluate the full benefit of the technique.

Power gating involves removing power from portions of the circuit when those portions are idle. This involves more than just switching off the power. It also involves signal isolation, so that inert portions do not pose unintended loads on other active portions. When used together, power switching and signal isolation can change an IC's timing dynamics, and if gated on or off improperly, can also affect functionality.