To accommodate foundry customers' 65nm designs, it is in everyone's best interest to fully leverage TSMC processes with compatible, power-saving EDA tools. TSMC already brings to bear low-power methodologies and IP aimed at reducing dynamic, active, and standby power leakage. All of these low-power methodologies require fully automated EDA support.

However, a fully optimized low power methodology requires more than just process support. It also requires that design tools in the methodology communicate low power design intent in a single, standard format. The Si2 Common Power Format (CPF), the first low-power EDA format embraced by TSMC for 65-nm low power design, enables this capability.

Ultimately, low power designs employ a variety of power reduction techniques such as power gating, multiple-voltage domains and dynamic voltage scaling. Because there are so many concurrent variables in designing with multiple techniques, TSMC has taken a phased approach to ensuring that automation of these techniques results in verifiable improvements to 65nm designs. This article describes an early program to validate the Common Power Format for use with TSMC technology.

The project

The objectives included:

• Validating the design technique in silicon, using CPF-based EDA tools
• Verifying functionality and timing results for the technique, as well as improving verification technologies
• Enhancing communications between logic design and physical design teams
• Looking for opportunities for further automation
• Achieving synergy between TSMC low-power IP and EDA tools for implementing power-gating and power shut-down circuitry.

In any design project, design intent must be clearly specified so everyone is on the same page. CPF automates this task by providing a single file with standard definitions of power intent. This allows designers and design tools to draw from a common data set all along the design flow. Once in place, this capability quickly makes it apparent that there might be more opportunities for driving CPF awareness into a low power methodology. To verify this, the project had to clearly spell out what techniques would be used (Figure 1).

1. The Boxed Area Defines TSMC's Low-Power Test Run.

The baseline for the project was a comparison to previous design techniques, without CPF support. The hypothesis that there would be dramatic improvement was safe; the impact of earlier power-reduction design techniques (e.g. area optimization and clock gating) on functionality and timing was minimal, but so was the reduction in power. The advanced techniques now being applied, such as power gating, were also expected to impact functional and timing verification, so it was important to gauge that impact and work to minimize it to preserve high levels of validity.

The "proof" design
TSMC used a large block similar to advanced system-on-chip designs. It involved over 100,000 instances, 50 (RAM) blocks, and over 100,000 nets.

In the design flow, we used CPF-enabled EDA tools, but we purposefully minimized the power-aware design techniques to a single subset: power-gating. This allowed us to better evaluate the full benefit of the technique.

Power gating involves removing power from portions of the circuit when those portions are idle. This involves more than just switching off the power. It also involves signal isolation, so that inert portions do not pose unintended loads on other active portions. When used together, power switching and signal isolation can change an IC's timing dynamics, and if gated on or off improperly, can also affect functionality.

More on CPF at 65nm
IP Usage
The project used a TSMC 65LP library. With Cadence CPF-enabled tools, we captured the proof design and proceeded through the design flow shown (see Figure 2). There were a few special low-power IP in this library — a requirement for this type of low-power design. These included specialized power-gating cells that would allow both column-style power gating and ring-type power gating. The specialized power switches automatically eliminate power-up glitches and electromigration through dual control and a dual-switch structure. An important part of the project was to validate that the CPF-enabled EDA tool could take proper advantage of these IP elements.

2. Flow of automation from RTL to GDS.

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As expected, the design was automatically augmented with power switches and isolation cells to accomplish power gating. In the flow, the RTL synthesis used power-gating auto switching inserted as a checkerboard or surrounding floorplan (Figure 3). We used NCSim for RTL simulation to verify power gating and retention flip-flop behavior. Then, NCSim gate-level simulation was done under power-mode transition and "X" propagation to simulate power shutdown for verification. Unknown "X" signal generation and propagation was done automatically in the CPF environment without Verilog model changes in the library.

3. Power-gating inserted surrounding the floorplan.

Before final commitment to silicon, we used Cadence Conformal and Conformal LP to formally verify the auto-control signal setting for the switches and isolation cells, as well as the actual power/ground connection to the network. In a typical traditional flow, designers would have to manually check the connections and generate large amounts of verification testbenches to check for functional correctness-- all error-prone activities. The use of an automated formal verification technique from design intent, through RTL and final implementation, is one of the visible benefits of CPF as used throughout this flow.

Results
When compared with the baseline project that did not involve CPF-based EDA tools, but did employ earlier low power design techniques, the current project revealed clear benefits. For instance, the design was completed faster, and required fewer iterations. In addition, because design intent was consistent throughout the flow, the integrity of the power gating structure was preserved throughout the design. Most importantly, the design achieved its overarching objective, which was a clear reduction in leakage power. Using the automated power gating technique, this design achieved 40x reduction in leakage power.

It was assumed that the pilot project would unveil some areas for further refinement, and this proved to be true. But the primary observation from the project was the variety of opportunities to enhance low-power design techniques through the use of a CPF-based format. This work is already under way in ongoing projects between TSMC and Cadence.

In addition, there were instances where the power/ground connection for the ring-type power gating technique, using the newest library IP, required some minor enhancement to the tool to better leverage the IP design. However, in no case did we find that CPF-based automation created a functional or timing failure, nor did automation of these techniques lead to area inefficiencies.

With the success of this first project, the two companies began work to refine and integrate IP design using the Common Power Format. In addition, we were able to validate CPF support for TSMC Reference Flow 8.0, which was announced in June 2007. This flow supports CPF tools for 65nm and 45nm process technologies.

In addition, TSMC and Cadence have embarked upon numerous CPF-based low power follow-on projects. These projects focus on complex low-power design techniques such as hierarchical voltage islands, adaptive-voltage scaling and power gating with data retention, as well as support for TSMC's new 45nm processes.

About the Authors:
LC Lu is Deputy Director of Design Methodology Program at TSMC, and George Kuo is Group Director of Technical Marketing at Cadence Design Systems.