Design Article
Define drain-current conditions when calculating power for multi-core SoCs
Arun Mishra, Freescale Semiconductor
1/5/2012 12:20 AM EST
Test case
Once the previous five run conditions were identified, a multi-module Run-Idd test case was developed. The SoC was configured in LSM mode with CPUs operating at 180 MHz with I/D-cache enabled, executing complex FFT code with the signal-processing engine enabled, and checkerboard patterns on complete SRAM. The various modules enabled in the Run-Idd test case were ADC, eDMA, FEC, external bus interface (EBI), LinFLEX, watchdog timers, system timers, DDR controller, FlexCAN and DSPI. After performing the required system and module initializations, all of these modules and the CPU were configured to execute respective data transfers continuously in an infinite loop.
All the typical Run-Idd conditions discussed above should be clearly mentioned in the datasheet as shown with a line entry in Figure 4 here:
Power measurement conditions and setup
Publishing the datasheet with the final current numbers requires a thorough analysis by executing the defined Run-Idd scenario on SoC across process, voltage, and temperature. Generally, there are three samples selected each from slow, fast, and typical corner lots, two voltage conditions (nominal and maximum operating voltages, 3v3 and 3v6), and three temperature conditions (-40, 25, 125C).
The following are some of important considerations to be considered to reduce the impact of setup related issues affecting the power numbers.
One of the major challenges which one may face during the power measurement exercise is related to the leakage numbers measured on silicon across process and temperature.
This is seen when, for a given corner lot sample at the same voltage, the current numbers vary largely with temperature due to leakage. In our case, we observed that at -40C, the core current was ~550 mA and it shot to ~1A at 125C. Of course, the Run-Idd activity would not cause the current to shoot up by twice from -40 to 125C. Therefore, it is important to know the expected leakage numbers for each corner lots samples under measurement. This can be done by simply holding the part in reset and measuring the current on each supply pin across temperature.
The graph of Figure 5 below shows the relation between leakage and Run-Idd numbers on a particular supply pin at 25C and 125C.
Conclusion
As with the other parameters in the datasheet, publishing maximum power numbers requires thorough background work, which we call here, "defining the typical Run-Idd conditions." This is an important activity to complete before starting the measurements. This feature discussed the various Run-Idd conditions, the details about measurement setup, and the effect of leakage current on the power numbers. Having the power numbers calculated with all the considerations discussed in this paper allows realistic values that can be provided for customers.
References
All the figures and results discussed in this paper are carried on a Freescale PowerPC based dual-core SoC meant for automotive safety applications. This device is yet to be released in the market, therefore the part number is not available.
Arun Mishra is lead design engineer at Freescale Semiconductor.
Once the previous five run conditions were identified, a multi-module Run-Idd test case was developed. The SoC was configured in LSM mode with CPUs operating at 180 MHz with I/D-cache enabled, executing complex FFT code with the signal-processing engine enabled, and checkerboard patterns on complete SRAM. The various modules enabled in the Run-Idd test case were ADC, eDMA, FEC, external bus interface (EBI), LinFLEX, watchdog timers, system timers, DDR controller, FlexCAN and DSPI. After performing the required system and module initializations, all of these modules and the CPU were configured to execute respective data transfers continuously in an infinite loop.
All the typical Run-Idd conditions discussed above should be clearly mentioned in the datasheet as shown with a line entry in Figure 4 here:
Figure 4 Power parameter in a typical datasheet
Publishing the datasheet with the final current numbers requires a thorough analysis by executing the defined Run-Idd scenario on SoC across process, voltage, and temperature. Generally, there are three samples selected each from slow, fast, and typical corner lots, two voltage conditions (nominal and maximum operating voltages, 3v3 and 3v6), and three temperature conditions (-40, 25, 125C).
The following are some of important considerations to be considered to reduce the impact of setup related issues affecting the power numbers.
- When SoC is configured to operate in external regulation mode, make sure that a proper compensation mechanism is put in place to ensure that the voltage drop caused by board trace impedances is compensated, and the final voltages reaching the supply pins are as desired for SoC operation. For internal regulation mode, the compensation is controlled by the internal regulator, but the drop should be manually compensated for the non-regulated supplies.
- The power consumption calculation for a device is based on the formula:
Total Power = I1 * V1 + I2 * V2 + I3 * V3 + …..
Where I1 is the current measured on voltage V1, I2 is the current measured on voltage V2, and so on.Therefore, connect an ammeter of the desired range on every supply pin of the SoC. By desired specifications, it is meant that if a supply pin shows a current of the order of µA, make sure that the range of the ammeter is properly selected to provide a realistic measurement.
- One should make sure that the power consumption occurring due to external board components is ruled out during the power measurement for SoC. This can otherwise give false power numbers for datasheet. In particular, current on VDD_IO supply is affected due to external board consumption.
One of the major challenges which one may face during the power measurement exercise is related to the leakage numbers measured on silicon across process and temperature.
This is seen when, for a given corner lot sample at the same voltage, the current numbers vary largely with temperature due to leakage. In our case, we observed that at -40C, the core current was ~550 mA and it shot to ~1A at 125C. Of course, the Run-Idd activity would not cause the current to shoot up by twice from -40 to 125C. Therefore, it is important to know the expected leakage numbers for each corner lots samples under measurement. This can be done by simply holding the part in reset and measuring the current on each supply pin across temperature.
The graph of Figure 5 below shows the relation between leakage and Run-Idd numbers on a particular supply pin at 25C and 125C.
Figure 5 Leakage impact on power number
As with the other parameters in the datasheet, publishing maximum power numbers requires thorough background work, which we call here, "defining the typical Run-Idd conditions." This is an important activity to complete before starting the measurements. This feature discussed the various Run-Idd conditions, the details about measurement setup, and the effect of leakage current on the power numbers. Having the power numbers calculated with all the considerations discussed in this paper allows realistic values that can be provided for customers.
References
All the figures and results discussed in this paper are carried on a Freescale PowerPC based dual-core SoC meant for automotive safety applications. This device is yet to be released in the market, therefore the part number is not available.
Arun Mishra is lead design engineer at Freescale Semiconductor.
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