Design Article
IC supplier, customer cooperation methodologies drive up electronics system quality
Yorgos Christoforou, Khaled Terras, and Roger Habets, NXP Semiconductors
7/13/2012 3:00 AM EDT
With increasing complexity of automotive electronic systems, one of the most important winning features of modern integrated circuits is quality. This trait is what most IC customers recognize and expect. Although IC manufacturers have been extremely successful in reducing defects, on the other hand a significant part of the quality drive for printed-circuit-board module makers is originating from reducing electrical over-stress (EOS), electrostatic discharge (ESD), and cases of no-trouble-found (NTF) (see below).
Contrary to manufacturing related issues, problems related to system EOS/ESD robustness or marginal/intermittent performance cannot be solved by the IC supplier alone. Solution of these difficulties requires the involvement of the PCB module maker and the car manufacturer as well. This is because the conditions leading to these types of failures can only be understood in the context of the application where the IC originally failed.
This article describes the way IC manufacturers may address EOS/ESD/NTF issues by working closely with customers. As part of this process, customers are engaged into cooperation around these specific failure modes during tailored workshops where running issues are analyzed in depth. After identifying all relevant details, containment actions are derived and permanent solutions are sought, based upon a Plan-Do-Check-Act (PDCA) loop. The cooperation continues in the frame of Quality Update Meetings, until all issues are closed permanently.
Value proposition
The large fraction of EOS/ESD/NTF (or in short EEN) issues in the supply chain and their inter-boundary nature should trigger the IC manufacturer to create a structured approach to actively focus on the following targets:
Failing-Parts-Per-Million (FPPM) reduction
As PPM is a major quality performance indicator in the electronics business for both the IC supplier and the PCB-module maker, it is essential to reduce it over time in a controlled way. Note that 1 FPPM (one failing-part-per-million failure rate) product inside a car that contains 10,000 parts would lead to 1% of cars of this type failing. This is not acceptable.
FPPM reduction can only be achieved collaboratively, through information exchange. Given the present trend of continuously increasing complexity in electronics, quality levels that were good-enough yesterday are no longer sufficient today. The new era of sub-FPPM (hence FPPB – Failing-Parts-Per-Billion) quality is about to commence.
Rootcause analysis throughput time (TPT) reduction
Because in customer support services time is money, rootcause analysis throughput time is a key parameter for any quality professional. Reducing analysis throughput time helps the entire supply chain to eliminate unnecessary cost and increase customer satisfaction.
The benefits from this approach can be summarized to be:
Reduction of quality costs: The amount of bottom line savings increases exponentially as one moves upwards along the supply chain from the IC supplier to the car maker. Keep in mind, the costs of poor quality related only to EOS/ESD could easily reach 5% of the turnover; for a 200M€ business the actual losses due to EOS/ESD can reach the 10M€, a considerable amount. Similar amounts are spent for servicing NTF issues.
Freeing-up a considerable amount of resources: Hence resources can be allocated to more profitable activities like R&D, or process improvements. A low complexity EOS/ESD issue can keep an R&D team busy for approximately 400 man-hours whereas NTF rootcause analysis can end up costing 1,000 man-hours.
Acceleration of the PDCA loop: By optimizing throughput time and efficiency, rootcause analysis can happen close to the source (to the environmental conditions in which the failure originally appeared), leading to an acceleration of the complaint-handling PDCA loop. This creates a lean infrastructure on which to perform rootcause analysis extending from the IC manufacturer to the car maker.
- EOS is any kind of electrical overload resulting in damage or malfunction of an electrical component or system.
- ESD is a specific type of EOS originating from triboelectric or inductive charging and encountered in manufacturing environments or applications.
- NTF is a category that contains cases of failures that appear only under very specific functional and environmental conditions which have been impossible to reproduce by the analyst and as soon as these conditions cease to exist, the failing behavior disappears.
Contrary to manufacturing related issues, problems related to system EOS/ESD robustness or marginal/intermittent performance cannot be solved by the IC supplier alone. Solution of these difficulties requires the involvement of the PCB module maker and the car manufacturer as well. This is because the conditions leading to these types of failures can only be understood in the context of the application where the IC originally failed.
This article describes the way IC manufacturers may address EOS/ESD/NTF issues by working closely with customers. As part of this process, customers are engaged into cooperation around these specific failure modes during tailored workshops where running issues are analyzed in depth. After identifying all relevant details, containment actions are derived and permanent solutions are sought, based upon a Plan-Do-Check-Act (PDCA) loop. The cooperation continues in the frame of Quality Update Meetings, until all issues are closed permanently.
Value proposition
The large fraction of EOS/ESD/NTF (or in short EEN) issues in the supply chain and their inter-boundary nature should trigger the IC manufacturer to create a structured approach to actively focus on the following targets:
Failing-Parts-Per-Million (FPPM) reduction
As PPM is a major quality performance indicator in the electronics business for both the IC supplier and the PCB-module maker, it is essential to reduce it over time in a controlled way. Note that 1 FPPM (one failing-part-per-million failure rate) product inside a car that contains 10,000 parts would lead to 1% of cars of this type failing. This is not acceptable.
FPPM reduction can only be achieved collaboratively, through information exchange. Given the present trend of continuously increasing complexity in electronics, quality levels that were good-enough yesterday are no longer sufficient today. The new era of sub-FPPM (hence FPPB – Failing-Parts-Per-Billion) quality is about to commence.
Rootcause analysis throughput time (TPT) reduction
Because in customer support services time is money, rootcause analysis throughput time is a key parameter for any quality professional. Reducing analysis throughput time helps the entire supply chain to eliminate unnecessary cost and increase customer satisfaction.
The benefits from this approach can be summarized to be:
Reduction of quality costs: The amount of bottom line savings increases exponentially as one moves upwards along the supply chain from the IC supplier to the car maker. Keep in mind, the costs of poor quality related only to EOS/ESD could easily reach 5% of the turnover; for a 200M€ business the actual losses due to EOS/ESD can reach the 10M€, a considerable amount. Similar amounts are spent for servicing NTF issues.
Freeing-up a considerable amount of resources: Hence resources can be allocated to more profitable activities like R&D, or process improvements. A low complexity EOS/ESD issue can keep an R&D team busy for approximately 400 man-hours whereas NTF rootcause analysis can end up costing 1,000 man-hours.
Acceleration of the PDCA loop: By optimizing throughput time and efficiency, rootcause analysis can happen close to the source (to the environmental conditions in which the failure originally appeared), leading to an acceleration of the complaint-handling PDCA loop. This creates a lean infrastructure on which to perform rootcause analysis extending from the IC manufacturer to the car maker.
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Dr DSP
7/26/2012 7:20 PM EDT
This is a very useful methodology that can also be applied to a variety of mixed systems. Hardware shipped for software development, IP Cores for use in FPGAs, etc. I wonder if these companies are using a similar technique. Anyone know?
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