Electrical over-stress and electrostatic discharge (EOS/ESD)
The field of EOS/ESD is a complex one, mainly due to the multiple mechanisms that may lead to such events. To assure that no latent damaged parts are ever delivered to customers, IC manufacturers must spend a continuously increasing effort in screening outlying devices during wafer-test (WT) and final-test (FT) using advanced techniques like for instance the Moving Limits. In the frame of the EOS/ESD/NTF program, companies can take this one step further by teaming up with PCB module makers to reach even lower zero-defect targets.
In the frame of this cooperation the following points are addressed:
Development of EOS/ESD robust systems:
Cooperation on EOS/ESD starts during the design phase in the form of module design and layout reviews. EOS/ESD is a failure mode that depends strongly on the design of the module. The latter should be able to resist all types of EOS, such as ESD (electrostatic discharge), EMI (electromagnetic interference), LU (latch-up), OVS (over-voltage stress), or any other type of electrical misuse [see Ref. 1]. These are aspects to be considered during design phase since the protection strategy and components have to be timely chosen.
Troubleshooting manufacturing facilities:
Under this category are found EOS/ESD process capability investigations of customer manufacturing facilities. Although manufacturing facilities may be designed to follow the IEC61340 or S20.20 ESD recommendations, ESD control target levels have to continuously be updated (reducing trend) for the assembly facilities to be able to cope with (1) the continuous miniaturization of the IC manufacturing processes and (2) the increase of the package dimensions to accommodate more complex integrated systems [see Ref. 2].
Design for testability for EOS/ESD:
Being able to verify whether a module has been pre-damaged during the module assembly process, specific leakage current tests can be included in the in-circuit test (ICT) or end-of-line test (EOLT) during module assembly. The data can then be used to perform advanced screening as, for instance, Part-Averaging-Testing (PAT) as recommended by the Automotive Industry Council (AEC) in the AEC-Q100 specification or Moving Limits, which is a more efficient technique.
Another similar but more thorough approach is to perform leakage tests at the beginning and then at the end of the test program. This allows better detection of damages introduced during testing itself. For the above tests to be implemented care has to be taken from the design phase of the module so that accessibility to the required module nodes can be guaranteed.
Fast and cost-effective rootcause analysis through self-diagnostics and failure signature comparison:
An interesting property of EOS and ESD IC failure signatures is that they repeat themselves over time to a level such that they allow a significant statistical analysis to be performed. As an example, 90% of the EOS/ESD failures of a LIN transceiver during car manufacturing carried exactly the same electrical failure signature for a large number of car makers. Using this information, the electrical fingerprint of the failure can be used with very high confidence to recognize the failure mechanism easily already at car manufacturing. The consequence is that the rootcause analysis throughput time seen by the car maker can be reduced from some weeks down to some hours (see below).
Rootcause analysis throughput-time is reduced by using "fingerprint" recognition.
No trouble found (NTF)
There are several possible rootcauses for having a technical-complaint classified as NTF. Many different situations can make the module fail but when the incriminated IC is tested separately, it looks to be good.
There are two very critical steps that should be followed to avoid this:
Failure isolation (FI):
On a failing module containing sometimes hundreds of electronic components, one needs to isolate the electrically failing devices. Some examples of failure isolation techniques [see Ref. 3] are: In-circuit-test electrical verification, functional-test verification, visual inspection, X-ray, thermal imaging, Time Domain Reflectometry (TDR), impedance measurement, and curve tracing measurement. The purpose of these techniques is to pinpoint the electronic components in a system that are really failing electrically and not due to a global failure of the system. These devices should then be selected for further analysis.
Failure confirmation (FC):
Once the actual failing devices are localized, a test called the ABA swap test is used as the ultimate verification for the failing device being at the origin of the system’s failure. In an ABA swap test the suspected IC is removed from the failing module and is placed in a known-good module. If the failure follows, the IC is confirmed as valid failure. However, in practice some aspects of the ABA swap test make it unattractive for customers:
- Desoldering and resoldering the ICs to a known-good module requires the use of very tight soldering/desoldering guidelines and ESD precautions. The analyst worries that the IC may get damaged and the precious failure information may be lost.
- The analyst worries that important failure mode information may disappear after the part has been submitted to soldering/desoldering.
- Reproducing the failure requires significant efforts from many disciplines and as the exact amount of time needed to reproduce the failure is not known, one is quickly brought in front of a dilemma: Complete the ABA preanalysis or send the part back to the supplier for a full analysis? Usually the second solution is followed; the part is shipped to the IC supplier for analysis.
However, statistical analysis shows that only 30% of the NTF cases were found to be real failures. The remaining 70% could not be confirmed by either the IC supplier or the PCB module maker upon return of the part. This example suggests that there is a lot of space for improving the pre-analysis of those components at the first place.