Design Article
Using bullet-proof isoSPI data links to boost battery-management systems
By Jon Munson, Linear Technology Corp.
1/29/2013 1:05 PM EST
Partitioning the BMS electronics
The example circuitry shown in Figures 2 & 3 follows the centralized architecture that is relatively typical of current BMS designs. The centralized structure however, does not fully utilize one of the primary isoSPI capabilities, namely operating with lengthy exposed wiring. Since conventional SPI connections are not suitable for this duty, present battery systems had to be specifically tailored to the communication limitations in the electronics. With isoSPI solutions, these design constraints are eliminated and a better mechanical optimization can be achieved.
Figure 4(a) (above, left side) shows a distributed daisy chain BMS structure that allows the pack to be arbitrarily modular and function as a distributed network. The network may have as many ADC devices (LTC6804-1) and harness-level interconnects as needed to satisfy the desired distribution of circuitry. The use of isoSPI networking for ADC information means all the data processing activity can be consolidated into a single microprocessor circuit that need not even be co-located with any of the battery units at all. This total networking flexibility allows an isoSPI-based BMS system to be designed for both high-performance and improved cost-effectiveness.
Figure 4(b) (above, right side) shows a distributed BMS structure that uses the isoSPI in a multidrop bus. While externally similar to Figure 4(a), including the vehicle wiring aspects, the isoSPI transmission-line is actually a continuous signal pair that parallels all the ADC devices (up to sixteen LTC6804-2) and terminates only the ends of the bus. Some of the bus is actually resident within a module, but ultimately leaves again to propagate to the next module.
One detail to note in the figures is that whenever an isoSPI segment is exposed to harness-level conditions (and thus subject to BCI interference testing), a small common-mode-choke (CMC) is placed in the connections with the associated isoSPI ports on the ICs involved. The CMC is a very small transformer element that completes the rejection of any residual very-high-frequency (VHF) common-mode noise that may leak through the inter-winding capacitance of the coupling transformer. Additionally, harness wiring is fully isolated for complete safety.
Meeting New Challenges
Since the isoSPI structure allows the minimization of electronics that is resident within cell modules, new directives like ISO 26262 are more easily and cost-effectively addressed. Take redundancy aspects for example, one can simply add extra copies of ADC sections and add them to the isoSPI network as needed. Also, with the consolidated processor functionality afforded by the networking approach, it is a simple matter to provide redundant data paths and even dual processors without major packaging impact, just add additional circuitry in the various modules as needed to achieve the reliability targets.
Conclusion
By integrating tried-and-true data communication techniques, isoSPI provides a robust and simple means of remotely controlling standard SPI devices that formerly required an extra protocol adaptation to CANbus. The isoSPI two-wire data link is a cost effective way to improve the reliability and structural optimization of Battery Management Systems through flexible networking of the ADC’s. Consolidation of the processor function away from the cells enables simplification of pack modules, thus minimizing the per-cell electronics content.
About the author
Jon Munson is senior applications manager with Linear Technology Corp., supporting its signal conditioning product line. He has a BS in electrical engineering and computer science from Santa Clara University. He has designed hardware for instrumentation, video, and communications products. Jon’s hobbies include hi-fi audio, aviation and do-it-yourself projects, as time permits while raising his two daughters.
The example circuitry shown in Figures 2 & 3 follows the centralized architecture that is relatively typical of current BMS designs. The centralized structure however, does not fully utilize one of the primary isoSPI capabilities, namely operating with lengthy exposed wiring. Since conventional SPI connections are not suitable for this duty, present battery systems had to be specifically tailored to the communication limitations in the electronics. With isoSPI solutions, these design constraints are eliminated and a better mechanical optimization can be achieved.
Figure 4(a) (above, left side) shows a distributed daisy chain BMS structure that allows the pack to be arbitrarily modular and function as a distributed network. The network may have as many ADC devices (LTC6804-1) and harness-level interconnects as needed to satisfy the desired distribution of circuitry. The use of isoSPI networking for ADC information means all the data processing activity can be consolidated into a single microprocessor circuit that need not even be co-located with any of the battery units at all. This total networking flexibility allows an isoSPI-based BMS system to be designed for both high-performance and improved cost-effectiveness.
Figure 4(b) (above, right side) shows a distributed BMS structure that uses the isoSPI in a multidrop bus. While externally similar to Figure 4(a), including the vehicle wiring aspects, the isoSPI transmission-line is actually a continuous signal pair that parallels all the ADC devices (up to sixteen LTC6804-2) and terminates only the ends of the bus. Some of the bus is actually resident within a module, but ultimately leaves again to propagate to the next module.
One detail to note in the figures is that whenever an isoSPI segment is exposed to harness-level conditions (and thus subject to BCI interference testing), a small common-mode-choke (CMC) is placed in the connections with the associated isoSPI ports on the ICs involved. The CMC is a very small transformer element that completes the rejection of any residual very-high-frequency (VHF) common-mode noise that may leak through the inter-winding capacitance of the coupling transformer. Additionally, harness wiring is fully isolated for complete safety.
Meeting New Challenges
Since the isoSPI structure allows the minimization of electronics that is resident within cell modules, new directives like ISO 26262 are more easily and cost-effectively addressed. Take redundancy aspects for example, one can simply add extra copies of ADC sections and add them to the isoSPI network as needed. Also, with the consolidated processor functionality afforded by the networking approach, it is a simple matter to provide redundant data paths and even dual processors without major packaging impact, just add additional circuitry in the various modules as needed to achieve the reliability targets.
Conclusion
By integrating tried-and-true data communication techniques, isoSPI provides a robust and simple means of remotely controlling standard SPI devices that formerly required an extra protocol adaptation to CANbus. The isoSPI two-wire data link is a cost effective way to improve the reliability and structural optimization of Battery Management Systems through flexible networking of the ADC’s. Consolidation of the processor function away from the cells enables simplification of pack modules, thus minimizing the per-cell electronics content.
About the author
Jon Munson is senior applications manager with Linear Technology Corp., supporting its signal conditioning product line. He has a BS in electrical engineering and computer science from Santa Clara University. He has designed hardware for instrumentation, video, and communications products. Jon’s hobbies include hi-fi audio, aviation and do-it-yourself projects, as time permits while raising his two daughters.
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