Optimum Design via 'Smart' Partitioning
Communications systems continue to grow increasingly complex as product-development times shrink. As designers look to mix and match circuits either on single systems-on-chip or on chip set broadband solutions, they are challenged to integrate the mostly analog front-end circuits with the mostly digital processing circuits on one chip. What elements should one integrate, and how does one partition the design for maximum efficiency?
This article will highlight some of the design decisions made by Cogency Semiconductor, a broadband-communications system provider, and how it applied a "smart-partitioning" philosophy to optimize the system design using one of Analog Devices Inc.'s mixed-signal front-end devices.
Cogency has developed a HomePlug 1.0-compliant home power line network interface chip set that takes advantage of smart partitioning. The chip set includes the Cogency CS1100 HomePlug MAC/PHY and the Analog Devices AD9875 broadband modem mixed-signal front end (MxFE).
Cogency's success hinged on the ability to optimize the overall system architecture while meeting performance, cost, power, size and time-to-market objectives. The starting point for system-partitioning decisions was found by looking at the relative complexity of the large-scale digital processing portion of the application vs. the mixed-signal/analog portion.
With that in mind, the fundamental aspects of scaling in analog and digital circuitry, the availability of existing silicon core portfolios and the cost/performance capabilities of different process nodes were used to determine the appropriate partitioning and overall level of integration.
The HomePlug specification defines a high-performance home-networking technology that uses in-house power lines as the transmission medium and provides Ethernet-class performance, whole-house coverage, built-in quality-of-service and privacy. Target applications include PC network adapters; residential gateways, including set-tops; and a range of entertainment and communication devices. Market requirements imposed these constraints on the reference design:Power consumption of less than 2 watts. This was driven by the bus-powered USB HomePlug adapter application and reflects power supply inefficiencies.
Low bill-of-materials (BOM) cost.
A small form factor for size-constrained applications such as wall-mounted Ethernet-to-HomePlug bridge devices and PC motherboards.
A working demonstration platform that meets performance targets within four months of the HomePlug specification release.
All design considerations were geared toward achieving those four targets, with an eye toward the path to future-generation products.
The HomePlug power line network interface consists of a media access controller (MAC), digital physical access controller (PHY), codec and analog signal-processing blocks (Fig. 1). The combined MAC/PHY function has complexity on the order of millions of transistors running at clock speeds in multiples of 50 MHz. Based on the complexity and performance requirements, and keeping a strong focus on minimizing die area and power consumption, we determined that the optimum process geometry was 0.18 micron. The choice also anticipated hitting the 0.18-micron process in the optimum part of its life cycle, but being entirely digital, the MAC/PHY is easily migrated to processes with smaller feature sizes.
Although not all of the carriers are used, the 128 carriers called out in the HomePlug specification span a bandwidth of 25 MHz. To support that bandwidth, both the transmit and receive paths must be sampled at a minimum of 50 Msamples/s. The high peak-to-average ratio of the orthogonal frequency-division multiplexed signals places dynamic-range requirements on the D/A and A/D converters that approach 10 effective number of bits. A wideband amplifier is needed to drive the 10-dBm transmit signal onto the line, which has an assumed nominal impedance of 50 ohms. Transformer coupling provides isolation from the power line. No hybrid function is required, because the HomePlug specification employs time-division duplexing. To maximize the available dynamic range of the A/D, receive path filtering and gain functions are used, including a bandpass filter to remove interferers such as AM or ham-radio signals and wideband noise. Finally, a programmable-gain range of about 40 dB is required to compensate for the large attenuation that can occur between networked nodes.
When looking at alternatives for the programmablegain amplifier (PGA), Cogency was dissatisfied with the discrete solutions found. Low-noise variable-gain amplifiers met the performance requirements, but they are typically expensive bipolar devices that consume significant power. Low-cost CMOS PGAs suffer from high-input referred noise and require a unique serial peripheral interface. A discrete implementation with switches and discrete amplifiers consumes a great deal of board area and is expensive and difficult to manufacture.
The Analog Devices AD9875 MxFE contains a transmit path interpolation filter and low-power D/A core, a receive path low-pass filter, a PGA and a 10-bit A/D. The converters met all of the performance requirements for the application. The integrated PGA has an input referred noise of 17 nV/the square root of Hz and a gain range of -6 to 36 dB, with a 2-dB step size. The integrated PGA was well-suited to the task and would provide significant advantages in terms of BOM cost, size and manufacturability over any of the discrete alternatives.
Despite the suitability of the AD9875, Cogency carefully examined the merits of alternative partitioning and single-chip integration scenarios before making a decision to use the AD9875.
Technologists find single-chip solutions sexy, but ultimately cost and performance are what drive decisions. One option considered was moving the analog circuitry onto the same process that was used to fabricate the large-scale digital signal processing. There are several issues involved in migrating mixed-signal circuits from 0.35 to 0.18 micron that are not present in an all-digital design. The most prominent are:
Lack of portability. Mixed-signal circuits do not port well, and the porting effort from 0.35 to 0.18 micron would have meant a complete redesign.
Reduced supply voltage. Lower supply voltages necessitate lower signal levels, which reduce the signal-to-noise ratio (S/N) for any given noise floor. To recapture the S/N, the noise floor must be lowered. In sampled data circuits, the noise floor is determined by the kT/C noise of the sampling circuits, and hence larger-value capacitors would be required.
Immature device models. The mixed-signal circuits required in this application, with device models that act subtly different than the silicon, would have increased the risk of missing critical performance targets.
Despite those limitations, it is important to examine the advantages that a single-chip solution could offer:
Device cost and board area. A single-chip solution eliminates chip-to-chip interconnections and the associated pins. The elimination of the second package also reduces board area. In the home-networking arena, small is good, but consumers will not pay a premium for it.
Board layout and EMI issues. The main culprits behind most EMI issues are high-speed digital buses. A single chip minimizes those buses and presumably will alleviate any EMI issues. Such issues were unlikely to arise, given the moderate speed of the interfaces.
Some factors that weigh against a single-chip solution are:
Silicon real estate premium. Because the size of the analog circuitry was likely to remain nearly constant in a port to 0.18 micron vs. 0.35 micron, the die area cost of the analog function would have increased substantially. That is because the wafer costs of the 0.18-micron process are currently, and are likely to remain, significantly higher than for the 0.35-micron process.
Digital coupling. Keeping the analog circuitry isolated from the digital circuitry is a daunting task. This was considered a significant risk in delivering first-pass silicon that met the analog signal-processing performance targets.
Silicon test yields. Larger dice inevitably have lower yields than smaller ones. In general, combining two functions of equal die size and independent yields of, for example, 90 percent and 80 percent will have a combined yield of their product of 72 percent. Keeping those functions separate will result in a combined yield equal to their average of 85 percent. The cost penalty in this case is then the ratio of those percentages-18 percent.
Chasing the process node. Increasing digital-circuit complexity and higher volume will be motivation to move to finer-pitch geometries, to lower the cost of the digital-circuit functions. In that case, staying with a single-chip solution means another nontrivial analog port to the new process node.
Ultimately, we decided that a single-chip solution may never be the optimal solution for this or other, similar broadband modem applications.
In working with Cogency and others, Analog Devices found that one of the priorities of the MxFE design was to look at the entire BOM and minimize the external-component count as much as possible. One area where that opportunity existed was in the design of the transmit path. By providing a transmit path D/A with a sample rate high enough to support 2x oversampling, the external reconstruction filter could be simplified. Cogency, by increasing the sample rate from 50 to 100 Msamples/s, was able to drop its analog TX filter from sixth-order to third-order, resulting in a significant reduction in parts count.
Another goal of the system design was to ease the interface between the digital PHY/MAC ASIC and the MxFE. By partitioning the buses running at lower rates, EMI, power consumption and pin count can all be reduced.
This was realized on the AD9875 by integrating the digital interpolating low-pass filter onto the device along with an input data demultiplexer. We divided the 10-bit bus running at 50 MHz and let the doubling of the sample rate happen on the MxFE, just prior to the D/A.
The die area that this arrangement consumed was small, but it made the interface half as wide (5 bits at 100 MHz) compared with the 10-bit bus that would have been required if the interpolation filtering was done on the digital PHY ASIC.
Applications engineer Brian Harrington at Analog Devices Inc. (Norwood, Mass.), and technical product marketing head Michael Burgener at Cogency Semiconductor (Toronto) hold BSEEs from the University of Massachusetts and the University of Waterloo (Canada), respectively.
Copyright 2002 CMP Media LLC
2/1/02, Issue # 14152, page 14.