Harness speed, performance, signal integrity, and low current advantages of 65nm QDR family SRAMs

Table 1 highlights the features and differences between the 65 nm and 90 nm QDR device families
(Click on table to enlarge)

Faster Operating Frequencies

Devices based on 65 nm technology are capable of operating at higher operating frequencies of 550 MHz and total data rates up to 80 Gbps. This results in significant bandwidth improvement (~23%) over 90 nm devices which operate up to a maximum frequency of 450 MHz. This improvement in operating frequency satisfies the higher bandwidth requirements of next-generation networking applications.

Lower Power Consumption

QDR devices based on 65 nm technology have lower power consumption than equivalent 90 nm devices. Worst case power savings is ~30%, with higher efficiency under typical operating conditions.

Improved Data Valid Window    

The data valid window for the outputs of 65 nm QDR devices is about 21% wider than that for 90 nm QDR devices and helps achieve better timing margins. This improvement is achieved using a low jitter clock generating a PLL (Phase Locked Loop) as opposed to the DLL (Delay Locked Loop) used in 90 nm technology devices. The PLL filters the incoming jitter and corrects any duty cycle distortion for the inputs. Figure 1 compares the data valid window of a 90 nm QDRII+ and a 65 nm QDRII+ device at 500 MHz. As shown, there is a significant improvement (~21%) in the data window for the 65nm QDRII+ devices.

Improved Signal Integrity

QDRII+/DDRII+ devices based on 65 nm technology have on-die termination for inputs such as data inputs, byte write signals, and input clocks (K/Kb). This feature is not present in 90 nm technology QDRII+/DDRII+ devices. On-die termination eliminates the need for external termination resistors thereby reducing the cost and power consumed by external resistors. It also improves signal integrity, simplifies board routing, and reduces the board area.

Lower Input and Output Capacitances

Compared with the 90 nm predecessors, the 65 nm QDR family of SRAMs has lower input and output capacitance by 60 percent. This translates to lower return loss and therefore lower reflections or discontinuity at the inputs. A lower capacitance also results in lower AC power consumption at the input.

Design Changes to Migrate from 90 nm to 65 nm Family

The 65 nm QDR family of devices provides a higher speed path for most applications. Developers can implement certain design changes that enable existing designs to transition seamlessly from 90 nm to 65 nm QDR devices:

Board Changes

For higher performance, the board should be designed to perform at speeds up to 550 MHz.

Host Controller Changes

Echo clocks need to be used to latch read data. If the existing design uses a K or C clock for the read data capture, then the host controller design must be changed to use echo clocks because this yields better timing margins for higher frequencies. The memory controller software should also be modified to accommodate the PLL lock time of 20 µs in the 65 nm technology device compared to the DLL lock time of 1024 clock cycles for the QDRII/DDRII and 2048 clock cycles for the QDRII+/DDRII+ devices in the 90 nm family.

Pinout Changes

In QDRII devices, the pins P6 and R6 are used as C and C# clocks. In 90 nm technology QDRII+ devices, P6 is used as the QVLD pin and R6 is a NC (No connect). In the 65 nm technology node, the QDRII+ devices are offered in two flavors: ODT enabled and ODT disabled devices. No change needs to be made when migrating from a 90 nm QDRII+ device to a 65 nm technology ODT disabled QDRII+ device as the pinouts are identical. However, when migrating from a 90 nm technology QDRII+ device to a 65 nm technology ODT enabled device, the Ball R6 is an ODT pin instead of a NC (No Connect). The ODT pin is used to select high range or low range of impedance for the inputs.

QDR devices based on 65 nm technology provide the ability to achieve high performance and bandwidth with few changes to existing boards. They also have the capability to support new designs and applications. This is possible by designing boards and host controllers to support high performance up to 550 MHz and 80 Gbps bandwidth in next-generation designs so there will be no changes to the existing boards or host controllers.

About the Author

Jayasree Nayar, holds a Master's degree in Electrical Engineering (VLSI design) from Santa Clara University of California, and joined Cypress Semiconductor in 2003. Jayasree is a Senior Applications Engineer working in Cypress' Memory and Imaging Division. Jayasree's responsibilities include creating, testing and maintaining signal integrity and behavioral models of key products, debugging technical issues, creating documentation, application notes and white papers, technically defining new product requirements, conducting system analysis to better understand how and where devices are being used, and board-level-failure-analysis debugging.