Tips and Trends: Implement design process changes to meet demands of LTE/LTE-Advanced

LTE and LTE-Advanced, standardized by the 3rd Generation Partnership Project (3GPP), is an evolutionary advancement of today’s mobile communication technologies such as GSM and WCDMA/HSPA. The primary goal for LTE/LTE-Advanced is to serve the surging demand for mobile broadband data by increasing peak and average data throughput, as well as significantly reducing latency while being limited by the available frequencies.

What is the implication for the semiconductor industry? One trend is for sure: the complexity calls for a change in architecture. Single-core solutions are being replaced by multi-core solutions, simple bus structures will be replaced by more complex memory and interconnect architectures, and the devices will have many I/O capabilities built in. And embedded software is a key element of any chip design project. 

A second trend, closely related to this, is the change in the design process. This involves doing different things as well as doing things differently.  Here are a few examples:

- Architecture analysis prior to any implementation has not only grown in importance, but also in complexity. Traditional approaches based on paper and pencil or spreadsheets no longer apply. The trend is clearly towards simulation-based architecture analysis. This requires simulation models as well as a more efficient infrastructure to perform the what-if-analysis since there are now thousands of scenarios that need to be analyzed.

- Modem designers must meet the requirements of the standard, while coming up with differentiating algorithms. They must rely on a testbench that guarantees the generation of standard-compliant signals. In addition, it must provide coverage of all the tests specified in the standards document and explore the possible options. Exhaustive simulation is the method of choice, and it requires the highest simulation performance, as billions of test vectors must be processed to analyze for standard compliance. In addition, multi-mode modems have become the norm rather than the exception. 

- IP reuse continues to increase. Whatever is considered to be a “commodity” will no longer be developed in house, but will be purchased from dedicated third parties. By 2014, the number of third-party IP blocks for wireless communication devices is expected to double, and will account for more than 50 percent of the chip. Integration of this third-party IP comes with its own set of challenges, including reliability, a proven legal framework and semiconductor process support. 

- Differentiation comes through the optimized implementation of dedicated accelerators. These might be optimized and tailored modem processors, or high-performance video accelerators. High-level design methodologies are now being applied, starting from a level of abstraction way above the classical register transfer level (RTL) coding style.

- Hardware and software will be developed and cross-verified in parallel. It is no longer possible to wait for the first hardware prototype before performing the initial integration testing and debugging. Today, virtual prototypes are being used to provide the embedded software developer an executable model of the to-be-developed hardware as early as the architecture gets finalized. The additional investment in the virtual platform pays off since it is available 6-9 months prior to the first hardware prototype. This enables more efficient software debugging and allows interaction between architects, software developers and hardware developers based on an executable specification rather than ambiguous paper specifications. Achieving first-day software bring-up on the first hardware prototype is the target objective.

- Verification accounts for more than 60 percent of the overall effort, meaning more efficient verification reuse throughout the design process is required. Taking the example of the modem, the standard-compliant signal generation should be reused as a testbench element whenever it comes to verifying the hardware / software implementation of this modem. 

Driven by complexity, “silo”-based design flows are coming to an end.  Architects, algorithm developers, hardware designers, software designers and verification engineers must interact very closely based on executable models that minimize ambiguity while providing integrated design and verification solutions from concept to final manufacturing, as well as production-proven semiconductor IP.  

As with any communication standard, LTE is about standard compliance. Therefore, there is an additional trend: the need to connect the front-end design process and the real-time test equipment. The motivation is obvious when you look at the task at hand. The real-time testing process is about generating standard-compliant input stimuli, running all the different test scenarios (which is typically done through thousands of different parameter configurations), and confirming that the design-under-test generates the expected result. This task is very similar to what is done during the algorithm design phase, the earliest phase in the design process.

Traditionally both tasks have been done in isolation. But given the complexity of standards such as LTE, there are good reasons to bring them closer together. One obvious motivation is the desire to compare results against each other, and the ability for cross debugging. This is even more valuable if you can rely on a cross-verification of the signal-generation used in simulation and the hardware equipment. Combined with the automatic parameterization of the hardware signal-generator from the simulation, this also significantly reduces time to first test and enables the reuse of all the test scenarios applied during the front-end design process.

The integration of the Synopsys algorithm design tools SPW/System Studio and Rohde & Schwarz signal generators is a good example of how to address this need. The solution combines the flexibility of a software-based approach and the real-time capabilities of a hardware-based approach. The result is a close interaction between algorithm designers and test engineers, all driven by one motivation: keeping up with the complexity of the standard.

About the Author

Markus Willems joined Synopsys in 1999 and is currently senior product marketing manager for System-Level Solutions, based in Aachen, Germany. Previous to that position, Dr. Willems was European marketing manager for verification and European technical marketing manager for System-Level Products. Before joining Synopsys, Dr. Willems was product marketing manager at dSPACE. He holds an MBA (Wirt-Ing.) from Hagen University and a Ph.D. (Dr.-Ing) and M.Sc (Dipl.-Ing.) in Electrical Engineering from Aachen University of Technology.