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steve5500
Regarding phase noise contributions and low-frequency offsets; it is correct ...
steve5500
The need for low wander (phase jitter below 10Hz) in telecom (SDH/SONET) ...
How to select the right timing device--A case for MEMS—Part I
Steve Pratt and Mehdi Behnami, SiTime Corporation
4/11/2012 10:31 PM EDT
When selecting components for a system, what is the first thing you think of? Chances are it is the microprocessor or another element that is central to the operation of your device. A timing device may be the last thing on your mind. Selecting timing components that operate at correct frequencies for the application may appear to be a straightforward process, however there are a number of factors to consider that affect system performance.
The clock signal is the heartbeat upon which all signals in the system are dependent. Timing components impact the performance of the entire system, so it is important to select them carefully, considering the requirements of each specific application. When selecting timing devices, and particularly when changing them in an existing design to improve performance, it is also important to consider the effect on overall design of the product and on the supply chain.
One of the primary building blocks for clock timing is the oscillator, consisting of a resonator and an oscillator circuit. Historically, resonators were made from quartz crystals connected to an analog oscillator circuit that drives the quartz to vibrate at the resonating frequency. Oscillators using micro-electro-mechanical system (MEMS) technology, whereby the mechanical resonator is built into a silicon wafer and packaged together with the oscillator circuit, have come into the market in just the past decade. MEMS-based oscillators offer many benefits in performance, reliability, and flexibility when compared to quartz.
Frequency and frequency stability
The basic parameter for any oscillator is its frequency. Oscillators are commonly available in frequencies ranging from kHz to several GHz. In the case of quartz oscillators, the quartz needs to be cut to precisely the correct size and thickness for a given frequency. Quartz oscillators are available in a limited number of standard frequencies and have to be produced to order if a non-standard frequency is necessary. This usually requires substantial volume, upfront NRE, and approximately a 16-week lead-time. In some cases, a quartz supplier may refuse to produce a non-standard device.
For MEMS oscillators, the same resonator is used for every frequency, and the specific frequency is determined by the electronics in the oscillator circuit. Since the circuits are programmable, any desired frequency is readily available. The frequency is independent of component size, an advantage that allows greater flexibility in board design.
Another important specification is frequency stability, or the variation from nominal clock frequency. Overall frequency stability, expressed in parts per million (ppm), consists of several components: initial tolerance, variation over temperature, variation with power supply voltage, variation with loading, and aging over time. The initial tolerance and temperature variation are the largest contributors to frequency stability. Table 1 shows frequency stability versus temperature for quartz and MEMS oscillators for a variety of frequencies. While some quartz oscillators exhibit excellent stability, tolerance for the MEMS oscillator is much tighter across all frequencies.

Table 1. Components of frequency stability for quartz crystal and MEMS oscillators measured across extended commercial temperature range (-20C - +70C).
Single-ended vs. differential
Chipset vendors may specify the required signal mode for timing chips, or the system designer may have some leeway. Single-ended oscillators are lower cost and easier to implement than those with differential outputs, but they have limitations. They are somewhat sensitive to board noise and are therefore typically best suited to frequencies below 166 MHz. Output types include LVCMOS, CMOS and LVTTL.
Differential signaling is a more expensive option, but it allows for more precisely defined timing and is preferred for higher frequency applications. Since any noise common to both differential traces will be zeroed out, this mode is less sensitive to external noise and generates lower levels of jitter and EMI. Figure 1 illustrates the power supply rejection ratio performance of several differential oscillators. Applications that benefit from differential signaling run at frequencies typically above 100 MHz and include servers, storage, telecom equipment, high-end printers, industrial equipment and FPGA-based systems. Outputs are usually LVPECL, but LVDS is an option for lower power applications.
Figure 1. Power supply rejection ratio (PSRR) of SiT9121 MEMS differential LVPECL clock compared to quartz oscillators. Source: SiTime measured data.
Jitter
Jitter, the deviation from an ideal clock signal, is one of the main contributors to system timing errors, so it is critical to account for the oscillator’s jitter when evaluating total timing budget. This is not necessarily a simple matter. Jitter requirements vary by application, and oscillator manufacturers do not all specify jitter in the same way.
RMS phase jitter is historically integrated over 12 kHz to 20 MHz offset from the carrier frequency, but this range is not appropriate in all cases. Most serial IO applications, for example, use a band-pass jitter filter to compute effective jitter. The lower cutoff frequencies of such filters range from 300 kHz to 6 MHz, while the upper cutoff frequencies range from 2.5 MHz to 20 MHz. Choosing a clock to meet the jitter requirements for these applications requires integrating phase noise over the appropriate range.
Historically, phase-locked loops (PLLs) used in oscillator circuitry are another source of jitter in the system. However, some MEMS oscillator circuits include high performance fractional-N PLLs designed to output the precise frequency required with extremely low levels of jitter, comparable to or better than that of fixed-frequency quartz oscillators. Programmable, ring-based quartz oscillators exhibit greater levels of jitter, making them suitable only for low-precision applications.
Reliability
Integrated circuits are graded for reliability in units of mean time between failure (MTBF), expressed in hours. The equivalent reliability grade is called failure in time (FIT). FIT rate is simply a mathematical equivalent of MTBF, expressed as the product of 1x109/MTBF. Since MEMS oscillators use a silicon-based manufacturing process, they exhibit semiconductor-level reliability at around 500 Million-hours MTBF. 500M hours MTBF translates to a FIT rate of 2. Quartz oscillators are often rated at around 30 Million-hours MTBF. Oscillators that are designed by silicon manufacturers tend to have better reliability, as shown in Figure 2. Furthermore, 100% silicon oscillators tend to have the best reliability.
Figure 2. Quality and reliability (FIT rate comparison) of quartz verses silicon products. Source: Company quality-reliability FIT/MTBF data.
Oscillators are designed to operate reliably within a specified temperature range, typically commercial (-20 to +70°C) or industrial (-40 to +85°C). A few are rated for an extended range as large as -55 to +125°C. It is important to select an oscillator rated for the appropriate temperature range for the application. When exposed to changes in temperature, Quartz oscillators can exhibit activity dips, in which the oscillator stops functioning. This can be a serious problem in high precision applications. Therefore, if the customer is concerned about activity dips, it is necessary to test the components over the expected operating range, a step that adds cost. MEMS oscillators do not experience activity dips.
Figure 3. Vibration tolerance of MEMS verses quartz oscillators.
Vibration, especially near the resonating frequency, can also introduce phase noise and slightly worsen frequency stability as shown in figure 3. Proper damping or mounting can help limit the effects of vibration on oscillator performance. However specific MEMS resonators are an order of magnitude more resistant in shock and vibration due to their unique design.
Classes of oscillators
Several classes of oscillators are available to meet the specific needs of different applications. What follows is an overview of the different options available. We explain specific applications in more detail in Part II of this article. Figure 4 shows the various classes of oscillator arranged by frequency stability and price. Standard oscillators (XO) cover a wide range of frequencies and are suitable for some industrial, consumer electronics and computing applications, where precise frequency stability is not required.
Figure 4. Various classes of oscillator by frequency stability and price.
For applications such as networking, GPS, and mobile devices with internet connectivity, improved frequency stability across the operating temperature range is important. For these applications, it is best to use temperature compensated oscillators (TCXO) to minimize the variation in frequency stability due to temperature shifts. Fixed-frequency quartz TCXOs below 50 MHz can achieve good temperature stability across -20 to +70 °C, but MEMS TCXOs can cost-effectively offer frequency stability down to ±0.5 ppm across the entire industrial temperature range (-40 to +85°C).
Voltage controlled oscillators (VCXO) are especially useful for clock synchronization for telecom and broadband applications. The output frequency is "pulled," or fine-tuned by up to ±200 ppm for quartz or up to ±1600 ppm for MEMS. VCTCXO oscillators incorporate both voltage and temperature control for telecom, networking and wireless products.
Spread spectrum oscillators (SSXO) may be helpful in cases where EMI is a major concern. Spreading out the oscillator frequency over a wider range reduces the peak of radiated energy while not adversely affecting performance. This technique is commonly used in processor, memory and some serial I/O clocking applications.
Sometimes it may be necessary to have a clock with changeable outputs for multi-protocol systems. MEMS oscillators can incorporate multiple frequency selection within a single device, which is not possible with quartz.
In Part I of this article we have discussed the key parameters affecting oscillator performance, including frequency, frequency stability, signal mode, jitter and reliability. We have explained that while both MEMS and quartz oscillators can be designed to meet required specifications for some applications, the programmability of MEMS oscillators enables greater flexibility and the addition of features and classes of oscillators not available in quartz. Part II will delve deeply into application-specific design criteria and important practical aspects to consider when selecting timing devices.
About the Authors
Steve Pratt holds the position of Director of Marketing at SiTime. Steve has been in the semiconductor business for more than 20 years and prior to SiTime, has worked for various analog semiconductor companies including Maxim, Micrel, and Monolithic Power Systems. Steve holds a BS degree in Industrial Engineering & Technology.
Mehdi Behnami, Director of Product Marketing at SiTime, has over 20 years experience in the semiconductor and electronics industry. Prior to SiTime, Mehdi held management and engineering positions spanning marketing, applications and research. Mehdi received his Master’s degree in Electrical and Computer Engineering from the University of Iowa.


Matthew.Isaacs
4/15/2012 5:46 PM EDT
This article fails to note that integration range is not necessarily related to corner frequency. Just because the corner frequency is at 1 MHz does not mean that jitter below that frequency can be ignored in the least. In fact, because many common RX circuits in high-speed serial links implement only a first order filter, and due to a digital frequency architecture that does not have the sensitivity necessary to respond to low or slow frequency changes, the jitter might grow much more quickly at lower offset frequencies than the clock recovery can possibly track, resulting in an eye closure or bit-error ratio penalty.
For example, 10UI of jitter at 1/100th of the corner frequency of a receiver's tracking bandwidth is as damaging to the bit error ratio of a first-order receiver at 0.1UI of jitter above the corner frequency.
For most quartz-based clocks, low frequency clock jitter can be conveniently ignored entirely, particularly if the clock is shared by circuits on both ends of a (short / low-delay) serial link. However, many serial link standards assumed quartz crystal based performance when the jitter tolerance requirements were developed. This is particularly true for point-to-point datacom standards. If in fact low frequency jitter is more significant than obtained using quartz-based oscillators, these assumptions are not valid, and the standard is incapable of providing adaquate guidance in terms of either system design or test conformance.
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steve5500
4/20/2012 12:41 AM EDT
Regarding phase noise contributions and low-frequency offsets; it is correct that jitter contribution at low offset frequencies cannot be ignored, and that was not the intended point in this article. The confusion seems to be in definition of “corner frequency”. The corner frequencies cited in the article refer to the 3dB upper and lower cutoff frequencies of a bandpass filter. The attenuation in stop-band is 20dB/dec for most standards, as the reader noted. The integration range is typically much larger than pass-band frequency range of the filter, for example, 100Hz to 50MHz (or half the clock rate). The full details can be found in SiTime application note AN10012: http://www.sitime.com/support2/documents/AN10012_SerialIO_PhaseJitterReguirement_rev1.2.pdf.
The 12kHz to 20MHz integration range does not assume any smooth filtering of phase noise outside that range; it totally ignores any phase noise outside that range. It is true that for cases that 12kHz to 20MHz phase jitter is low, the filtering response of the application can be ignored because the noise outside the application filter pass-band would be small. Nevertheless, the application filter response is the one governing the jitter budgeting of the application and 12kHz to 20MHz integrated phase jitter is merely a proxy that has been widely used in practice.
SiTime's new class of LVCMOS, LVPECL, and LVDS devices meet low typical phase jitter of 0.5ps (0.85ps max) integrated from 12kHz to 20MHz. The user can easily use these parts regardless of analysis method used.
The standard governing phase jitter filtering and budgeting has been developed for a long time with careful attention to different trade-offs. One of important jitter documents for serial-IOs is MJSQ that was generated for Fibre Channel applications. To my knowledge, the MJSQ does not make any assumption about the oscillator source.
Steve Pratt
SiTime Marketing
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Matthew.Isaacs
4/15/2012 5:47 PM EDT
Serial link standards that recognize the reality of low-frequency jitter accumulation in multi-hop links have been developed. Examples include ITU-T SDH requirements for STM-64 links, which requires 10Gbps receivers to handle up to 2490 UI of jitter at 10Hz modulation frequency. As datacomm is now attempting to become like SONET & SDH in terms of being able to share timing across the network by passing it along from one node to the next in a long chain, the considerations of low-offset phase noise are becoming extremely important for both traditional telecom and datacomm.
All of this means that those who advocate MEMS over quartz should at least publish a phase noise plot in their attempts to produce a case that MEMS can provide an acceptable replacement to quartz-based oscillators. Even better would be for them to publish test results of "wander" -- meaning jitter below 10Hz. With the communications industry's seismic shift towards synchronized networking to support realtime audio & video, this is the hot topic, not high-frequency jitter, which has already been conquered by the venerable 10 cent quartz crystal & a sub-cent oscillator circuit contained within any IC that may need a clock.
I should note that unlike the authors, whose jobs appear to rely upon selling MEMS, I have no financial ties to anything in the quartz realm -- I simply need to be able to use a clock that works.
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steve5500
4/20/2012 12:34 AM EDT
The need for low wander (phase jitter below 10Hz) in telecom (SDH/SONET) applications and convergence of telecom and networking through Synchronous Ethernet is expected to increase demand for parts with low wander. This is true. The topic of wander was not addressed becasue it's beyond the scope of this article.
The question is whether MEMS oscillators can deliver on that, and the answer is yes. SiTime has published phase noise plots on their website (starting from 1kHz offset) for specific frequencies. In addition, SiTime provides phase noise plots down to 1Hz for any specific frequency that a customer may request. As a guideline, the RMS wander for SiTime's SiT8208/9 and SiT912x single-ended and differential MEMS-based oscillator products is 1.5UI rms (phase jitter between 1Hz to 10Hz). This easily meets the 2490UI tolerance limit the reviewer mentions. Furthermore, SiTIme's upcoming MEMS-based Stratum-3 devices will meet all MTIE and TDEV requirement for synchronous networks.
Steve Pratt
SiTime Marketing
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awaretek
4/19/2012 12:08 PM EDT
As Mathew Isaacs points out above, this article is very misleading, in that it shows only data favorable to MEMS resonators and avoids the large and serious disadvantages of MEMS vs. quartz resonators.
In fact, MEMS have such terrible short term stability that MEMS manufacturers like SiTime avoid the subject entirely. It turns out that MEMS resonators have problems for which there were previously no specifications defined, since quartz simply doesn't have those particular problems, such as extremely large numbers of continual frequency jumps as large as 1 PPM. That's why MEMS Manufacturers like the authors always like to talk about averages, such as integrated phase jitter (with carefully chosen ranges to show "good" results), instead of showing a good old fashioned phase noise plot that would show the horrible phase noise performance of MEMS, particularly close in to the carrier where it often matters most. The reason is because MEMS have much lower "Q" or quality factor, than quartz, which is why quartz has always been used for precision time and frequency instead of mechanical resonators.
A more balanced source of information can be found at http://www.pletronics.com/ple/pages/documentation (I have no affiliation with Pletronics, the publisher of the data sheets such as AN# 801: Comparative Analysis: MEMs versus Traditiional Quartz Oscillators - that offers a balanced comparison of the two technologies.
It is unfortunate that marketing so often over-rides engineering and common sense these days.
Ron Stephens
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cmathas
4/19/2012 2:00 PM EDT
See replies from the author on Part II of the article at
http://www.eetimes.com/design/communications-design/4371124/How-to-select-the-right-timing-device-Part-II?Ecosystem=analog-design
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psevalia
4/19/2012 8:50 PM EDT
Hi Ron - are you the Director of Sales and Marketing at Q-Tech Corporation, a supplier of quartz crystal oscillators? http://www.q-tech.com/contact.html
If so, I completely understand your perspective.
Please do see my comment below on how SiTime is providing correct data and information to our customers for them to make an informed decision.
Best regards
Piyush Sevalia
VP, Marketing, SiTime Corp.
psevalia@sitime.com
408-331-9138
www.sitime.com
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psevalia
4/19/2012 6:15 PM EDT
Hi Ron Stephens - the Pletronics article that you refer to, compares quartz oscillators with a first generation MEMS oscillator that was originally released in 2006, 6 years ago.
Four subsequent generations of MEMS oscillators have shown dramatic improvements in performance. In addition to the information in this article, please look at the technology section of the SiTime website. http://www.sitime.com/company/technology-overview/overview
Some performance specs of SiTime’s recent MEMS oscillators are:
500 fs of integrated RMS Phase jitter from 12 kHz to 20 MHz (SONET Standard)
5 PPB of Allan Deviation (short term frequency stability) which is about 500 times better than what was referred to in the Pletronics article. Please look at the datasheets of SiT820x, SiT500x, SiT912x, SiT530x for more details.
If you register on the SiTime website, you will also have access to performance measurement reports, here.
http://www.sitime.com/support/performance-measurement-report
These reports show measurements of specs for different frequencies such as phase noise, Phase jitter and period jitter, rise and fall time and duty cycle.
Also - if you have access to IEEE or ISSCC proceedings, please look at the ISSCC paper Session 11.6, presented on Thursday, Feb 21, 2012 for details on implementation on our new MEMS oscillators.
In the future, do look out for information on Resilience - how MEMS oscillators outperform Quartz on PSRR, Vibration Tolerance, EMI susceptibility and overall reliability. This information will be published on our website in the next 2 weeks and contains detailed results.
SiTime offers as much information as you need to make a decision on selecting the right timing component for your design. If you do not find this information on our website, then please do contact us at salessupport@sitime.com. We'd be happy to provide you with what you need.
Piyush Sevalia
VP, Marketing, SiTime Corp.
psevalia@sitime.com
408-331-9138
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