FPGAs over USB - Page 2.
It is the final method, which can be tweaked to offer the additional capability of configuring the FPGA over a USB interface. This configuration can be done in the serial or parallel data path of the FPGA. Once the FPGA has been programmed, the USB controller can revert back to its default functionality of implementing a simple data interface with a host computer.
Many of the USB controllers available in the market will contain a programmable CPU of their own which can perform some application-level functions in addition to implementing USB protocol level management. In order to load the configuration bit stream into the FPGA, the USB controller will have to generate the necessary configuration signals. There are multiple configuration methods to program each FPGA and any of these can be chosen by the USB controller to load the configuration bit stream.
In case of applications where human intervention is not always convenient (i.e., satellites and submarines), this method of reconfiguration will prove helpful since it does not require an on-site engineer to facilitate the task. For an advanced FPGA-based application that requires high-speed USB connectivity, configuring the FPGA over USB eliminates the need for a dedicated configuration chip (for example, a PROM or a processor) for the FPGA.
Upon power-on or on receiving a command from the USB host it is bound to, the USB controller would initialize itself into a state in which it awaits the bit stream from the host through the data endpoint. On receiving a bit stream with a valid signature, the USB controller would then proceed to reset the FPGA and generate the configuration waveform to load it with the bit stream. Once the configuration is successful, the USB controller would switch back to the data conduit mode.
Today, there is a high-speed USB controller chip capable of performing the multiple tasks required for configuring FPGAs over USB. It contains a GPIF controller block that can generate waveforms to interface with external ASICs, microcontrollers, or FPGAs. Vendor commands are sent from the host to initialize the GPIF controller whenever a firmware upgrade is required or when the device powers up. Once controller has entered the configuration mode and the GPIF controller is initialized, the host can send the configuration bit stream through an OUT endpoint. When the configuration is successfully, the host can send another USB vendor command to place the controller back into data transfer mode.
By enabling reprogramming over USB, existing FPGA systems can reduce system cost by eliminating the need for additional programming circuits to configure the FPGA.
About the Author
Gopalakrishnan V is a senior application engineer with Cypress Semiconductor. He holds a BA degree in Electronics and Communication from Anna University, India.