ARM adds 64-bit support to server system IP

LONDON – Processor intellectual property licensor ARM Holdings plc is announcing two pieces of system IP within its CoreLink family that are tuned to support system-chips for deployment in networking and server applications.

These are the CCN-504 cache coherent network with integrated level-3 cache and the DMC-520 dynamic memory controller that has been designed and optimized to work with CCN-504. These are intended to support the Cortex-A15 processor and the ARMv8 instruction set architecture that will yield 64-bit ARM cores in the future.

The CCN-504 I designed to extend the cache coherent multicore capability up to four, quad-core CPUs – so 16 cores – whereas the previous generation CCI-400 supported up to a maximum of 8 cores with cache coherency. In addition the CCN-504 supports heterogeneous computing through additional CPUs, DSPs and accelerators accessed through a non-coherent network interconnect.

The IP block can deliver up to one terabit per second of bandwidth via a 128-bit wide bus channel and provides a level-3 cache configurable between 8-Mbytes and 16-Mbytes.

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"CCN is for chips in enterprise-oriented network infrastructure and servers and server-type functions merging with communications networks," said Neil Parris, interconnect product manager with ARM.

The IP builds on the success of the Amba 4 ACE specification released in 2011 but supports dynamic frequency and voltage scaling (DFVS) in CPU clusters including big-little processor clusters and enables improved energy-efficiency and lower latency than software coherency. A snoop filter removes the need for broadcast coherency messaging, further reducing latency and power.




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The CCN-504 and DMC-520 in system-on-chip context. Source: ARM

"The CCN itself is generally a single clock domain that runs in the gigahertz range but it is possible to voltage-scale the interconnect fabric and there are retention modes," said Parris. He explained that CCN-504 logic can be switched off and a keep-alive voltage used to maintain the level-3 SRAM cache ready for power up.

The DMC-520 is a dynamic memory controller that has been designed and optimized to work with the CoreLink CCN-504. It supports DDR3, DDR3L and DDR4 DRAM and is part of an integrated ARM DDR4 interface solution incorporating ARM Artisan DDR4/3 PHY IP planned for introduction in 2013.

LSI Corp. (Milpitas, Calif.), a designer of chips for storage, networking and client computing, and server chip company Calxeda Inc. (Austin, Texas) are lead licensees for the CCN-504.

Designs are currently targeting 28-nm CMOS process technologies with 20-nm designs expected to follow, said Parris.


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