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Joe56

11/27/2012 11:09 AM EST

MRAM is a proven solution for protection of data in the event of system power ...

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Pramodh_Cypress

11/13/2012 1:20 PM EST

32Mb-128Mb will be on advanced technology nodes and should have reasonable die ...

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Using nvSRAMs for power-fail reliability in enterprise SSDs

Pramodh Prakash, Cypress Semiconductor

11/5/2012 12:10 PM EST

Use nvSRAM--Page 3.

Nonvolatile SRAM (nvSRAM)

nvSRAM combines two workhorse CMOS technologies into one device - SRAM and SONOS non-volatile technology. During normal power-on system condition, the nvSRAM behaves just like a conventional SRAM. The SRAM part of the IC performs random access read/write at speeds up to 20 ns access times, using standard Asynchronous SRAM signals and timing. But on a power glitch or fail, the intelligence in the chip detects the threat and automatically saves a copy of the SRAM data into non-volatile memory where it can stay unchanged for over 20 years. On power-up RECALL, the IC returns the data copy back to the SRAM and system operation can continue precisely from where it was left last giving you a fast SRAM that never loses data. The latest high density (16Mb) nvSRAMs are also available in high bandwidth DDR NAND Flash (ONFI 3.0/Toggle 2.0) interfaces as well.

The transfer between SRAM and non-volatile array inside is completely parallel (cell for cell) allowing the STORE operation to complete in 8 ms or less, without user knowledge. The IC family also provides user controlled software STORE and RECALL initiation commands, as well as a user controlled hardware STORE initiation command in most versions.

nvSRAM is a highly reliable product, manufactured in a high-volume, proven CMOS + SONOS process. In addition, it has more than 20 years of history in military, commercial, storage, medical, and industrial applications.

Figure 3 shows the concept of nvSRAM, which combines a fast SRAM element and a nonvolatile element into a single cell. Figure 4 shows the cell structure of the nvSRAM.

 

Figure 3: nvSRAM Concept

Figure 4: nvSRAM Cell

Nonvolatile SRAM – Asynchronous Solutions for Enterprise SSD

Figure 5 shows an asynchronous nvSRAM used as the nonvolatile buffer for Enterprise SSD data streams and metadata that needs to be backed up on power loss. The VCAP capacitor shown in Figure 5 powers the STORE cycle that moves data from SRAM to nonvolatile cells. VCAP is a standard capacitor of approximately 50 µF (see datasheets for details).

Figure 5: Enterprise SSD Asynchronous nvSRAM Solution

For new designs, asynchronous nvSRAM densities are available today from 256-kbit to 8-Mbit, with 16-Mbit devices being introduced in 2012.

Nonvolatile SRAM – Synchronous Solutions for Enterprise SSD

Figure 6 shows nonvolatile SRAM devices for Enterprise SSDs, based on the new Synchronous High bandwidth (up to 12.8Gbps) NAND interface nvSRAM. These devices will be available at 16-Mbit densities and are currently being sampled, with production in the first quarter of 2013.

Figure 6: Enterprise SSD Synchronous nvSRAM Solution

As explained earlier, a Supercapacitor or discrete bank of tantalum capacitors is used as a secondary voltage source to provide energy required for data transfer from SDRAM to NAND flash on power down.

This transfer from a fast volatile memory to a nonvolatile memory at power down uses the same concept that the Cypress nvSRAM invented 20 years ago. The difference is that the Cypress nvSRAM includes the power detect, data transfer management, fast volatile memory, and nonvolatile memory all in a monolithic IC. The data transfer is completed inside all memory cells at the same time using little power and taking only a few milliseconds. Meanwhile, the SDRAM to flash transfer is done at the system level using high-power I/O connections that can quickly drain a large capacitor and take a much longer time to complete.

The SSD controller in the Enterprise SSD architecture also supports the high-speed synchronous NAND interfaces to NAND flash (ONFI 3.0, Toggle DDR 2.0) devices. High-speed synchronous NAND interface is now supported in time-proven nvSRAM core technology, with industry standard ONFI 3.0/Toggle 2.0 interfaces, to provide Enterprise SSD makers a high performance synchronous nonvolatile memory solution. This new nvSRAM can sit directly on the NAND flash bus and become the active memory space for the critical nonvolatile data (see Figure 6). The new nvSRAM interfaces are being designed to the open standards, and will use standard commands and standard signal timing. This approach eliminates or minimizes the super capacitor/bank of tantalum capacitors and the data transfer logic, and gives the Enterprise SSD system a much shorter backup. Also eliminated are the reliability issues associated with the capacitor back-up solutions.

Enterprise SSDs require reliable and fast backup of critical data streams and metadata during power loss. The current capacitor back-up solutions have serious reliability issues. This article discussed the asynchronous nvSRAM solution and introduced a synchronous nvSRAM that can sit on the NAND flash bus. The nvSRAM provides reliable and fast back-up of critical Enterprise SSD data, eliminating the reliability concerns of super capacitors and the bank of tantalum capacitors in the process.

 

About the Author

Pramodh Tumkur Prakash is Senior Product Marketing Engineer at Cypress.  He has an M.S. in microelectronics with 7 years experience in Application/System Development.  He can be reached at tup@cypress.com.

 

 





DougInRB

11/6/2012 12:35 PM EST

How does an nvSRAM compare with the new MRAM technology in terms of cost and reliability? It seems that MRAM is ultimately a better solution, since it is non volatile, does not require a data transfer, and does not require a back-up power source. MRAM also has SRAM-like interfaces and timing...
Clearly, nvSRAM has an advantage in terms of density, but how much is actually required for a an SSD write cache?

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Pramodh_Cypress

11/8/2012 3:31 PM EST

nvSRAM is completely on the standard CMOS manufacturing process and this is a big advantage in terms of both cost, manufacturability and supplier reliability. MRAM, on the other hand is on a non-standard process, which translates to higher costs.
SSD write cache density would be in 100s of MBs to GBs range, but only a portion of that data (metadata) needs to be backed-up reliably on power loss and that is where nvSRAM solution comes in. Replacing all of the SDRAM write cache with nvSRAM would be the ideal solution. But, those densities are currently out of reach.

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Joe56

11/27/2012 11:09 AM EST

MRAM is a proven solution for protection of data in the event of system power loss because it is inherently non-volatile, there is no additional time needed to write data to a secondary non-volatile array, it simplifies the controller design, offers the speed of RAM and has superior endurance. MRAM is processed using standard CMOS base wafers to provide low cost as well as lower overall TCO to the user. Everspin, the leader in MRAM technology,announced customer sampling of the world's first commercial Spin Torque MRAM in a 64Mb density with a DDR3 interface. Now in one device the user can have power fail safety, non-volatility, DRAM DDR3 compatibility, with ultra low latency. With MRAM users can choose between SRAM like interface with existing products in volume production as well as look to the future with ST-MRAM in DRAM like interfaces.

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R G.Neale

11/6/2012 12:54 PM EST

Pramodh a couple of questions. What is the timeline for bit capacity greater than the 16-Mbit planned for production in the first quarter of 2013. What is the lithographic node for the 16-Mbit you (Cypress) are now sampling?
Looking at the future requirements of enterprise SSDs enterprise servers, what in your view is likely to be the bit capacity requirement for SRAM or your nvSRAM?
What is your view of PCM as a competitor for this SSD role?

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Pramodh_Cypress

11/8/2012 3:36 PM EST

Neale, 16Mb is planned for first quarter of 2013, with 32Mb in fourth quarter.

16Mb devices are on 130nm node.

Based on the future requirements and feedback from customers, the density requirement would be in the range of 32Mb - 128Mb.

We have not evaluated PCM as a major competitor. I will check on PCM and get back to you.

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cmathas

11/8/2012 1:31 PM EST

Stay tuned, I've let the author know that there are questions. They should respond shortly.

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lwang61

11/11/2012 11:31 PM EST

Would 32Mb-128Mb nvSRAM have incredible large die sizes using 130nm technology node?

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Pramodh_Cypress

11/13/2012 1:20 PM EST

32Mb-128Mb will be on advanced technology nodes and should have reasonable die sizes.

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