High-speed I/O--Page 3.
The issue here is really the concentration of the heat generation in a single chip. This makes thermal management much more complex compared to a system where this heat is spread over various chips. Also, it is not attractive to be constrained in the amount of digital functionality that can be implemented in a single (expensive) deep sub-micron ASIC by the power that is consumed in the interfaces.
Add to this the fact that the wafer cost of a smaller geometry CMOS process is higher than for a larger geometry, this means that the analogue part actually becomes more expensive. This is illustrated in figure 3 below, which shows the relative cost for digital and analogue functionality for different process nodes. While the digital cost reduces due to the die shrink due to the smaller geometry, the analogue cost goes up, as the size of this functionality is not reduced (but wafer cost goes up).
Figure 3: Relative cost of silicon for digital analogue functionality
So while the CMOS process shrink helps to reduce cost and power per gate for the digital parts, it actually increases the cost of the analogue functionality. For instance, the 100 port 10Gbps interface mentioned above would represent in excess of 20% of a 15mmx15mm chip real estate. This is not the best use of an expensive 40nm or 28nm wafer.
Additionally, extreme sub-micron processes are starting to suffer from higher leakage currents. This is something that can be mitigated in digital designs by targeted design techniques, but would add straight to the total power consumption of analogue designs. These considerations make these advanced processes not optimal choices for analogue functions associated with high-speed interfaces and high performance equalization.
A final cost consideration should be the wafer yield. Providing a decent yield for large complex digital chips is challenging in itself, but combining this with yield loss due to parametric failures on the analogue circuits would make these chips even more expensive. An alternative is to design the analogue functionality with extreme amounts of margin against the specification. However, this will significantly impact the expected performance of the high-speed interfaces.
When designing large SoCs companies often rely on proven IP blocks to reduce the risk of a design failing. Most ASIC suppliers dedicate significant resources to the development of advanced I/O cells. However, with process technology nodes being first optimized for high-density digital functionality, the implementation of high performance analogue circuit elements is done at high risk during the early phase of process development and volume shipments.
The development of any new product resides within and is dependent upon what is now fashionably termed the “Ecosystem”, as illustrated in figure 4. The ecosystem comprises all the elements necessary to make the application successful. Notwithstanding the availability of an end market for the product, a host of other technology and resourcing constituents are needed in order to realize the final product, many of these closely intertwined with the silicon process technology to be used.
Figure 4. SoC Ecosystem
In the case of mixed signal systems using a small geometry CMOS ecosystem a key element is the availability of high performance analogue IP, which always lags behind the high speed digital IP, as it is not the key driver for the technology. This lag will result in more risk being attached to time to market. Additionally it is rare to see both high-speed digital system design and analogue expertise combined in the same organization. This means that in many cases the analogue IP is required from outside of the organization, limiting the choice of suppliers and the ability to tailor precise offerings.
Design tools are another key element. Historically, full analogue/mixed-signal design kits for CMOS (130nm and below) have been very difficult to obtain. If a high performance 'digital' process is required then it is usual for no analogue kits to be offered. Analogue kits are released first for the 'generic' process options for mixed-signal support. In many cases the 'generic' process are too slow, too high a Vt etc. however since equalization functions are generally built around high-speed digital functionality, analogue support for such high-speed processes are a prerequisite.
Design kits supporting analogue design for low geometry CMOS have been proven to be crucial for first-time right designs. Basic design kit offerings may be more suitable to early process feasibility work, but not full-blown design efforts. This means that when high-performance analogue I/O functionality has to be combined with large digital blocks, leading edge processes cannot be used, as the design information for the analogue part is just not yet available.
Time to market/risk
As yet the performance of analogue designs in 40nm is not fully proven in production volumes. Whilst devices have been produced these are devices with digital functionality and have not provided analogue interfaces with any kind of complexity. This is as expected, as analogue chips often take a few iterations to get completely right. Many of these designs are functional at the first try, but are likely to miss some or many of the parametric specifications. Digital design however, is much better supported with design kits and CAD tools, often yielding first-time-right designs, even in new processes.