Lattice adds over 90 reference designs for PLDs

Lattice Semiconductor Corp. has released more than 90 reference designs optimized for the MachXO and ispMACH 4000ZE PLDs.  

The reference designs will speed the design and deployment of commonly used functions such as general purpose I/O expander, I2C bus master / slave, LCD controller and SD Flash controller, as well as other interfaces.

Coupled with complete documentation and design source code, the reference designs can be customized.

Each reference design consists of comprehensive documentation along with HDL source code (Verilog and/or VHDL) and test benches, many of which have been pre-implemented and validated using Lattice’s development kits.

Reference designs optimized for control applications, including I/O expansion, interface bridging, level translation and power-up sequencing using the MachXO family, have been validated using the MachXO Mini Development Kit, an easy-to-use, low-cost platform that accelerates the evaluation of MachXO PLDs.  

Using the preloaded mini system-on-chip (mini SoC) design provided with the development kit, designers can test within minutes I2C, SPI and UART interfaces in addition to the 8-bit LatticeMico8 microcontroller and low power sleep mode functionality.  

Designers can rebuild these demonstration designs using the free downloadable reference design source codes in less than one hour.

Alternatively, designers targeting low power applications can use reference designs optimized for the ispMACH 4000ZE family that have been fully tested and verified using the ispMACH 4000ZE Pico Development Kit, a battery-powered platform to accelerate the evaluation of ispMACH 4000ZE CPLDs.

 Using the preloaded ispMACH 4000ZE Pico Power demo design provided with the development kit, designers can test I2C master and LCD controller interfaces in addition to the embedded ispMACH 4000ZE oscillator timer, then build their own designs using the free downloadable reference design source code.

Lattice Semiconductor