EDA Design Features

AUTOSAR proof-tests vehicle electrical design at every level

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Model-driven development forestalls “11th hour” design problems

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Give the people what they want: HLS for RTL verification

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System Level Software Centric Power Debugging using Virtual Prototypes

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Making the most of the system level in analog design

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Accelerating the time to IC layout

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Generating AMD microcode stimuli using VCS constraint solver

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Power analysis of clock gating at RTL

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Using unified modeling methods to reduce embedded hardware/software development

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SPICE Simulation of Transmission Lines by the Telegrapher's Method (Part 1 of 3)

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Technical Papers

Board Design Guidelines for LVDS Systems

Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs

Critical Techniques for High Speed A/D Converters in Real-Time Systems, 6th Edition

Mixed Signal Power Management: Bridging the Analog-Digital Divide with Mixed Signal FPGA Graphical Design Configuration Methodology

Decentralized Trust Management for Securing Community Networks

The Dark Cloud: Understanding and Defending against Botnets and Stealthy Malware

Courses and Webinars

Designing Power Supplies for High-speed A/D Converter Applications

Low Power Solutions for Your Virtex-6 and Spartan-6 FPGA Designs

Latest MIPI Standards: PHY and Protocol Testing Guidance

Manufacturing-Aware Routing at 32/28nm

Accurate Power Analysis of Low Power Techniques Using PrimeTime PX

Realizing Today's 32nm and Beyond Large Capacity Designs

Fast 3D Field Solver Extraction with StarRC Custom Rapid3D Technology

RF Detectors Demystified

Seven Deadly Sins of Slow Software Builds

Utilizing Design Compiler 2010 Technologies to Double Synthesis and P&R Productivity

Teardowns

Micron drives process integration with 42-nm DDR3 SDRAM

Teardown: Inside the art of pulse oximetry

Eye-Fi uses Secure Digital (SD) card slot for Wi-Fi in cameras

Teardown: Inside Cisco's Flip UltraHD digital camcorder

UPDATE: B'com, Toshiba win sockets in iPhone 3GS

A first look inside the Palm Pre

What you need to know about Microsoft's BlueTrack mouse

Under the Hood: Android dreams, GooglePhone delivers

Sperry vertical gyro for Boeing 747

Evolution of handheld gaming, Part 1

More Design Teardowns >

Reference Designs

Quantenna debuts 802.11n 4x4 MIMO wireless video bridge ref design

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Commentary

The ripple effect

Ron Collett

Part of the reason so many semiconductor projects miss schedule is that staffing levels are not aligned with the level of complexity that the design team needs to undertake. This is solvable problem.

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Protect your goal with post-silicon formal verification

Lawrence Loh

SoC designers are learning the benefits of applying high-capacity formal verification techniques at every stage of the design. Our formal tools are powerful and versatile enough for a wide variety of tasks such as architectural exploration and RTL verification, all the way through post-silicon debug.

Join  post comment   2 comments    last comment  MHK_#1
I have to say I know and want to use formal verification method. I just don’t have an enough time to ...

Dispelling the myths of High-Level Synthesis

Brett Cline

High-level synthesis (HLS) has been a hot topic for about the last 10 years, characterized as Electronic System Level (ESL) synthesis, algorithmic synthesis, and behavioral synthesis, and C synthesis by some. I just call it “simply, a better way to design hardware.”

Join  post comment   4 comments    last comment  eewiz
I think the main problem with HLS is that, the implementation efficiency hasn't reached that of the ...

Semiconductor input costs vs output prices -- managing the squeeze

Walden Rhines

Increasing commodity costs and decreasing consumer prices place big pressure on profit margins. How can IC companies and EDA vendors manage the input costs/output prices squeeze?

Join  post comment   7 comments    last comment  Wally Rhines
The Gary Smith EDA – Proposed ITRS Cost Chart 2010 shows the combination of “Embedded Software ...

How productive is your R&D organization?

Ron Collett

Productivity drives development throughput in your R&D organization - the higher the productivity, the greater the throughput. And throughput is a measure of how much product the engineering organization churns out during a given period of time.

Join  post comment   4 comments    last comment  RCollett
I don't necessarily believe that rigid metrics increases throughput. Rather, metrics applied in the ...

Modernizing the peer code review process

Alen Zukich, Klocwork

As your software development processes evolve, so too must your code review practices.

Join  post comment   1 comment    last comment  KB3001
It's the constant pressure to bring new products to market at a faster pace that is driving people ...

Viewpoint: The coming tsunami in the electronics ocean

Rajeev Madhavan

In the vast electronics ocean, there’s a tsunami headed our way. EDA might well be able to catch the wave — with a little bit of savvy, ingenuity and engineering know-how.

Join  post comment   3 comments    last comment  Neo1
While the market for mixed signal design is large and growing the same cannot be said of the EDA ...

Debug will get your attention, sooner or later

Sean Safarpour

Debug will get your attention one way or another. If you give it attention early in the development cycle, it will reduce the amount of time spent on debug later and in future designs as well as reducing the uncertainty related to debug.

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Why debugging takes way longer than you'd think

Jit Lim

Intermittent failures are among the most difficult to solve-- and eat time--as this step-by-step analysis shows

Join  post comment   6 comments    last comment  WKetel
It is certainly true that intermittent failures are a large challeng. In this case, if they had been ...

The democratization of MEMS design and manufacturing

James Hogan

A perfect storm is brewing in semiconductor design and it reminds of a period about 20 years ago when many of the same forces were at work. The storm is all about challenges and opportunities to expand a market for a specific type of semiconductor technology, and the main thing missing is coherent infrastructure or ecosystem to facilitate it.

Join  post comment   2 comments    last comment  Robotics Developer
Having worked in the ASIC industry for 18+ years I can say that the challenge with MEMs is the ...

Recent Comments

Bob Lacovara  07.29.2010
Phase-change memory: A rebuttal of Micron’s article
This is an interesting topic, and it would be good to hear from Mr. Atwood. Perhaps he has reasons ...
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HajiShan  07.29.2010
Why a power-factor correction device is better suited to industrial applications
Fig 2 looks like a capacitive load, not inductive. Am I missing something here?
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drobesk  07.29.2010
EDA startup Sigasi raises funds
Sigasi, in their belief that they have added "intelligence" to their Integrated Development ...
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Most Commented

Why engineers don't like Twitter

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Employers getting more picky hiring engineers

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Motorola, Nokia, RIM, reject Apple antenna claim

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Opinion: Microsoft dying? Don't bet on it

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Why legislative mandates of engineering goals are a bad--and even dangerous--idea

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Noteworthy in Products

Microchip unveils smaller, more power-miserly op-amps

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