EDA DesignLine Highlights

join the conversation | start a forum

Global FDSOI ecosystem rising

What were they thinking: Confessing to an apparition

Penetration of Verification IP

DRC debugging challenges in AMS/custom designs at 20 nm

Semi market contracted in 2012

EDA/IP weekly roundup – May 22nd 2013

Collaborative Advantage: OpenDFM achieves production status

Preparing for DAC: Technical panels

Just in the nick of Tempus

Electromagnetic Interference (EMI) Pt 2

What were they thinking: exhibiting at DAC

Rapid progress in silicon photonics standards

How much of the chip does IP fill?

EDA/IP weekly roundup – May 15th 2013

EDA in the Cloud: OneSpin says your design is secure

Atrenta’s Ajoy Bose: 2nd rising of EDA

Moving to SystemC TLM for design and verification of digital hardware

What were they thinking: Your remains

What will the IP landscape look like in the future

Collection: Intellectual Property (IP)

EDA/IP weekly roundup – May 8th 2013

Sage solving an orphan EDA problem

A consumer reports methodology for IP

A new kind of IP company

Synthesis-aware clock analysis and constraints generation

EDA Design Features

More Design Articles >

Technical Papers

Clock and Reset Ubiquity: A CDC Verification Perspective

Break Through Your ASIC Prototyping Bottlenecks

Ten Things You Should Know about Verification IP

A smart integrated switch cell for well bias low power architecture

10 Ways to Reduce Time in Product Development

More Technical Papers >

Courses and Webinars

Power Architecture Solutions for Industrial Control

Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications

Fundamentals of Analog Verification

More Courses and Webinars >

Teardowns

CMOS power amplifiers penetrating 3G handsets

Intel's 22-nm process gives MOSFET switch a facelift

More Design Teardowns >

Reference Designs

Quantenna debuts 802.11n 4x4 MIMO wireless video bridge ref design

Quantenna Communications Inc. has debuted a complete reference design based on its QHS600 IEEE 802.11n wireless LAN (WLAN) 4x4 multiple input, multiple output (MIMO) chipset.
Learn more >

Lattice adds over 90 reference designs for PLDs

Lattice Semiconductor Corp. has released more than 90 reference designs optimized for the MachXO and ispMACH 4000ZE PLDs.
Learn more >

More Reference Designs >

Products

TI expands ecosystem for MSP430 Capacitive Touch solutions

Cadence launches massively parallel timing tool to speed SoC design

Cypress releases latest version of PSoC Designer IDE

Microchip expands 8-bit PIC MCU portfolio with intelligent analog

EFM32 "Wonder Gecko" with ARM Cortex-M4 and FPU

Altera Stratix V GX FPGAs achieve PCIe Gen3 compliance

QuickLogic's camera I/F solution for TI's ARM MCUs & Android Jelly Bean 4.1.2 OS

Aldec's Spec-TRACER for safety-critical FPGA & ASIC designs

Altera to acquire power technology innovator Enpirion

Intilop, Altera deliver unprecedented sub-microsecond full system latency

More Products >

Commentary

Crosby, Stills, Nash, and Donny

Clive Maxfield

A couple of evenings ago, I went to see Crosby, Stills, and Nash in a live concert – it was BRILLIANT!!!

post comment 5 comments last comment David Ashton
When I was in Zim I used to buy New Musical Express occasionally and drool over all the acts that ...

What were they thinking: Confessing to an apparition

Brian Bailey

This is an interesting patent in that it has some sensible elements and some that are are totally crazy...

post comment

Penetration of Verification IP

Brian Bailey

How does the market for verification IP compare to design IP...

post comment

DRC debugging challenges in AMS/custom designs at 20 nm

Srinivas Velivala, Mentor Graphics

The traditional DRC verification flow used by custom layout designers simply can’t provide the needed level of productivity when debugging DRC results at advanced nodes….

post comment

Semi market contracted in 2012

Brian Bailey

According to IDC, the semiconductor market contracted 2.2% last year although larger companies saw bigger losses...

post comment

EDA/IP weekly roundup – May 22nd 2013

Brian Bailey

Aldec, Avery, Berkeley, Cadence, Cypress, DAC, GlobalFoundries, IDC, Imec, Imperas, Mentor, Oasys, OpSIS, Real Intent, Renesas, Samsung, SEMI, Si2, Tezzaron and TSMC made the lineup today. See here for their news…

post comment

Collaborative Advantage: OpenDFM achieves production status

Steve Schulz

The OpenDFM standard has achieved production support status for process nodes down to 28nm, and development support through 20nm…

post comment

More Commentaries >

Reader Message Boards

News, Analysis, and Opinion

Global FDSOI ecosystem rising

Broadcom: Time to prepare for the end of Moore’s Law

Microchip’s MASTERs Conference for embedded-control engineers

Altera acquires TPACK; expands OTN solution capabilities

3-D interposers stack chips

TSMC starts FinFETs in 2013, tries EUV at 10 nm

China Fabless: Allwinner's secret to tablet IC success

Silicon Valley Nation: Memoir's CEO shift, new direction

China, India outspending U.S. in semiconductors

Tensilica acquisition to accelerate Cadence core strategy

More News >

EETimes 40th Anniversary iPad App celebrates the visionaries, technologies, and events which have defined the electronics industry.

Most Popular

1	Broadcom: Time to prepare for the end of Moore’s Law
2	Intel's new CEO shakes things up
3	High-tech jobs migrate
4	Intel pushes for more research beyond 10-nm
5	Slideshow: Maker Faire returns to Silicon Valley
6	Arduino board plugs DIYers into the cloud for $69
7	Teardown: Samsung Galaxy S4
8	Europe launches $12 billion chip support campaign
9	Intel Haswell packs integrated voltage regulator
10	Photo gallery: Engineering's messiest desks

Launch Box

	EE Times event coverage: Electronica 2012
	185 Million Normalized Electronic Parts
	See what's going on in Munich this year!
	Video Design Ideas
	Visit DesignCon Community and keep the conversation going
	All About Innovation

Signal integrity issues on the rise
Our virtual panel shares eye-opening advice for anticipating, detecting, and mitigating SI problems in faster, increasingly complex designs.
➔ View the latest digital edition of EDN
➔ Design feature: Why your 4.7-uF ceramic cap becomes 0.33 uF
➔ Teardown: Analog rules over digital in noise-canceling headphones
➔ Design Ideas: Two-IC circuit combines digital and analog signals to make multiplier circuit
➔ Tales From The Cube: Nonlinear transmission lines keep developer on the fence
➔ Pulse: The electronic brain gets closer

Meet the Editor

Hi, I'm Brian Bailey and I'm the editor of the EDA DesignLine. If you are interested in submitting a technical article, blog or product announcement, or just want to reach out say hello, you can call me at 503-352-4336 or email me at brian_bailey@acm.org.

Newsletter
A weekly newsletter is available which provides a round up of the latest technical articles, products and news from the EDA sector. Sign up here.

EDA DesignLine Highlights

EDA Design Features

Technical Papers

Courses and Webinars

Teardowns

Reference Designs

Products

Commentary

Recent Comments

Most Commented

Reader Message Boards

News, Analysis, and Opinion

Most Popular

Launch Box