EDA Design Features

Getting real (time) about embedded GNU/Linux

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Reproducing a Cray 1 supercomputer in a single FPGA

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Optimizing the manufacturing test program, data collection, and diagnosis for yield analysis

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Debugging the Linux kernel with JTAG

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Android, Linux & Real-time Development for Embedded Systems

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System Verilog configurable coverage model in an OVM setup – concept of reusability

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Reusability, usability and flexibility

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Reduce embedded SoC design cost & optimize IP integration

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FPGA compilation on-site or in the cloud

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What really limits MOSFET performance: silicon, package, driver or circuit board? (Part 2 of 2)

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Development of a Spice op-amp macro-model for current-feedback amplifiers (Part 2 of 2)

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Picking the right built-in self-test strategy for your embedded ASIC

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Development of a Spice op-amp macro-model for current-feedback amplifiers (Part 1 of 2)

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Using in-design physical verification to reduce tapeout schedules

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System level software centric power debugging using virtual prototypes

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Technical Papers

Power Integrity in Systems Design: Part 1

Sweet Sounding SoCs

6 Tips to Get Started with Automated Testing

Why Simulation Matters: A Case for Riviera-PRO

Guaranteeing Silicon Performance with FPGA Timing Models

Why Printed Circuit Board Design Matters to the Executive: How PCBs Are a Strategic Asset for Cost Reduction and Faster Time-to-Market

Courses and Webinars

Linaro 10.11 release and beyond

Addressing Software Challenges on Multi-core and Multi-chip Platforms

Editorial Webinar: High Performance RF and High Speed Dataconverters for Military Radio

Telepresence of Everyday Terminals

How to Verify the Data in Your LTE Downlink Signal

Conquering the Memory Bandwidth Bottleneck On-Chip

Theories, Techniques, and Validation of Over-The-Air (OTA) Test Methods for Evaluating the Performance of MIMO Handsets

Debugging High Speed Memory and Serial buses with Greater System Visibility

SSL Drivers Reliability – Dispelling the Myth on Poor Driver Reliability

Tips and Tricks for High Speed Printed Circuit Board Design

Teardowns

Micron drives process integration with 42-nm DDR3 SDRAM

Teardown: Inside the art of pulse oximetry

Ear bud headphones jam lots of complexity in a tiny package

Eye-Fi uses Secure Digital (SD) card slot for Wi-Fi in cameras

Teardown: Inside Cisco's Flip UltraHD digital camcorder

UPDATE: B'com, Toshiba win sockets in iPhone 3GS

A first look inside the Palm Pre

What you need to know about Microsoft's BlueTrack mouse

NAND Flash - The New Era of 4 bit per cell and Beyond

Under the Hood: Android dreams, GooglePhone delivers

More Design Teardowns >

Reference Designs

Quantenna debuts 802.11n 4x4 MIMO wireless video bridge ref design

Quantenna Communications Inc. has debuted a complete reference design based on its QHS600 IEEE 802.11n wireless LAN (WLAN) 4x4 multiple input, multiple output (MIMO) chipset.
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Lattice adds over 90 reference designs for PLDs

Lattice Semiconductor Corp. has released more than 90 reference designs optimized for the MachXO and ispMACH 4000ZE PLDs.
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More Reference Designs >

Commentary

DAC attendees reinforce need for industry events

Robert Smith

If exhibitors are looking ahead to DAC 2011, they are likely wondering how to connect better with designers and understand how they can better help them. At Magma, we decided the best approach was to ask them, and what we learned in our post-DAC survey of attendees will (we hope) serve as a useful guide to planning. We’ll share what we learned –– well, some of what we learned.

Join  post comment   3 comments    last comment  Nic_Mokhoff
The following response in the Magma survey goes to the heart of a well-produced and focused exhibit ...

Avnet and Actel offer great SmartFusion mixed-signal FPGA workshops

Clive Maxfield

Avnet Memec and Actel are hosting a series of one-day workshop that provide hands-on experience working with Actel's SmartFusion mixed-signal FPGAs and design tools.

Join  post comment   6 comments    last comment  SkiFaster
The Avnet Speedways were specific to North America, although they also ran events in Europe earlier ...

FPGA-to-ASIC conversion with zero NRE

Clive Maxfield

KaiSemi performs automated FPGA-to-ASIC conversion with Zero NRE, functional guarantee, and a very short cycle time; this is a full turnkey solution that is seamless to the customer.

Join  post comment   4 comments    last comment  Max the Magnificent
Hi there -- re your questions -- I don't know the answers yet -- but keep the questions coming and ...

Let's not adopt this bad habit of journalism

Bill Schweber

Good engineering combines data- and fact-driven analysis with experience, hunches, and a sense of what's going on.

Join  post comment   26 comments    last comment  Rich Krajewski
I forgot my conclusion! It was that, we need to be really cynical when reading technical news ...

How strong are your IP assets?

Thomas Marlow

There is no question that a portfolio of patents can provide tremendous value to a company. In fact, many will agree that trying to compete in a high technology industry without adequate patent protection is insane if not merely futile.

Join  post comment   10 comments    last comment  tmarlow
You are absolutely correct. This is indeed a first step in a large process (resources permitting). ...

EDA and Systems Design Converge...Or Do They?

Ron Wilson

System designers and IC designers seem to have little in common, but an interesting set of forces in bringing them into closer proximity.

Join  post comment   4 comments    last comment  rkpatil
As many of them echoed their sentiments the two design flows ( IC design and SW design) are still ...

The ripple effect

Ron Collett

Part of the reason so many semiconductor projects miss schedule is that staffing levels are not aligned with the level of complexity that the design team needs to undertake. This is solvable problem.

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Numetrics' fact-based planning solution can be applied to one project or numerous projects. The ...

Protect your goal with post-silicon formal verification

Lawrence Loh

SoC designers are learning the benefits of applying high-capacity formal verification techniques at every stage of the design. Our formal tools are powerful and versatile enough for a wide variety of tasks such as architectural exploration and RTL verification, all the way through post-silicon debug.

Join  post comment   3 comments    last comment  Alok78
Yes, it is all about ROI, which management will understand. Jasper’s approach to formal verification ...

Dispelling the myths of High-Level Synthesis

Brett Cline

High-level synthesis (HLS) has been a hot topic for about the last 10 years, characterized as Electronic System Level (ESL) synthesis, algorithmic synthesis, and behavioral synthesis, and C synthesis by some. I just call it “simply, a better way to design hardware.”

Join  post comment   5 comments    last comment  DKC
"The SystemC classes include the basic extensions necessary for accurate hardware modeling" - not ...

Semiconductor input costs vs output prices -- managing the squeeze

Walden Rhines

Increasing commodity costs and decreasing consumer prices place big pressure on profit margins. How can IC companies and EDA vendors manage the input costs/output prices squeeze?

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The Gary Smith EDA – Proposed ITRS Cost Chart 2010 shows the combination of “Embedded Software ...

Recent Comments

Patrick Perdu  09.09.2010
Three Things Every Programmer Should Know About RMA
Thanks for sharing your paper. I am not sure about why assumption 4 (on your page 4) is a problem: ...
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t.alex  09.09.2010
Echelon rolls Linux-based smart grid products
I wonder what is the main factor for choosing Linux here? Will the code be opensource ? Can outside ...
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Feory  09.09.2010
Protecting your intellectual property
In some cases, keeping an invention a trade secret is a viable option and might even be preferred ...
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Most Commented

Enter the EE Life August 2010 Cartoon Caption Contest

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Apple should build a fab

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Why China should bar Cisco, Moto and HP

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Opinion: Microsoft dying? Don't bet on it

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Mandating an FM radio in every cell phone: what are they thinking, and why?

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Can SMSC controller kick-start USB 3.0?

SMSC added graphics to the list of uses for the USB 3.0 interconnect in rolling out its ViewSpan controller.

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