Critical area optimizations improve IC yields

Density-driven wire spreading can be applied during global route and track assignment to achieve more uniform wire distribution and reduce areas with minimum spacing. Wire spreading can also be applied after the design is fully routed to further increase spacing between wires and reduce critical area as shown in figure 6.

Wire spreading — achieved by pushing wires off-track if space is available — creates a jog in the wire layout and increases the wire length. These changes to the wire layout and length can cause potential lithography issues and increase the probability of an open circuit.

Therefore, the router should not spread a wire unless the available space is larger than the minimum jog length recommended by the foundry, as shown in figure 7. To prevent timing deterioration, post-detail-route wire spreading should not push wires that are part of timing-critical nets.

Once the router performs yield optimizations, critical area analysis can validate that the total critical area has been improved and thus the yield has increased. The critical area heat maps in figure 8 show how the short critical area is reduced after wire spreading.

Figure 8 — Short critical reduction area after wire spreading.

Critical area reduction on a 90-nanometer design

To show how yield improvements can be measured during physical design, critical area analysis was applied to a 90nm design with 8 routing metal layers, 330K standard cells, 18 macros and 80 percent utilization.

The router performed critical area analysis on all metal layers and reported the results as a percent of the total chip metal layer. The results were used to guide post-detail route wire spreading to reduce the total critical area. The graph in figure 9 illustrates the critical area improvement after wire spreading.

Figure 9 — Critical area improvement after wire spreading.

Conclusion

Once an afterthought, yield is becoming a considerable concern for designers. It is now necessary to perform yield optimization during physical implementation so that optimizations can take place with no impact on timing, and other design targets.

Critical area provides an accurate and proven metric for defect-limited yield. Implementation tools that incorporate critical area analysis are best equipped to determine which routing optimizations can be applied to improve yield. A complete solution must incorporate three key elements:

• Fast critical area analysis engine applicable to implementation needs.
• Good quality correlation with foundries’ sign-off tools.
• Timing-driven yield optimizations for critical area reduction.

References

[1] Peter Van Zant, “Microchip Fabrication, A Practical Guide to Semiconductor Processing”, Chapter 6: Process Yields.
[2] “Test Yield Models”, http://www.semiconfareast.com/test-yield-models.htm.
[3] Way Kuo and Taeho Kim, “An overview of manufacturing yield and reliability modeling for semiconductor products”, proceedings of IEEE, 87(8):1329-1344, 1999.
[4] James A. Cunningham, “The use and evaluation of yield models in integrated circuit manufacturing”, IEEE Transactions on Semiconductors Manufacturing, 3(2):61-70, 1990.

Frank Lee is vice president of R&D for Synopsys, where he manages the place and route R&D group for Synopsys' physical design flagship products.

Atsuhiko Ikeuchi is manager, System LSI Division, Toshiba Corporation. Yoshiki Tsukiboshi is chief specialist, EDA Technology Development Department, Toshiba Microelectronics. Takashi Ban is specialist, EDA Technology Development Department, Toshiba Microelectronics.