New trends in constraint-based design promise to help design teams avoid missteps that have plagued complex custom design for years. Emerging design environments promise the flexibility that designers need to draw on the most appropriate tool, and degree of automation, that best fits the job at hand.

For semiconductor companies, continued market demand for more powerful portable applications means greater need for more cost-effective mainstream analog design, more advanced mixed-signal and RF system-in-package (SiP) designs, and more powerful system-on-chip (SoC) designs. With each product generation and new manufacturing technology, however, AMS designs face greater technical hurdles; each advance in process technology increases the type and number of constraints as seen from the number and complexity of design rules.(Figure 1).

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Figure 1: The increase in the number and complexity of design rules characterizes the rapid advances in IC manufacturing technology.

For mainstream AMS IC designers working in 130nm technologies, growing difficulties in maximizing both design performance and manufacturing yield require greater accuracy in modeling and simulation, to reduce guard bands without compromising yield. For custom mixed-signal designers targeting 90nm process technologies, issues related to signal integrity complexity and timing closure require more effective methods to address potential yield problems well before manufacturing.

Design challenges further escalate with advanced SiP and next-generation 65nm SoC designs that combine complex digital blocks with RF components for wireless consumer devices. As clock frequencies increase and IC feature sizes shrink, designers must deal with increasing analog-like behavior even from digital blocks, and growing challenges in integrating analog, digital and packaging requirements in these complex designs. At next-generation 45nm technologies, these challenges escalate even more rapidly for designers working to characterize cell libraries quickly and accurately.

Designers already need more effective methods to manage parasitic behavior complexity, thermal and process variations, and noise interactions. Similarly, as they cope with the growing use of multiple power-supply regions, designers will require greater precision in transistor optimization and layout for high-speed I/O, noise control and significant IR drop due to parasitics.

Overcoming limitations
For semiconductor companies, the increasing mutual influences between design and manufacturing place further strain on scarce design resources. Semiconductor companies typically find only one AMS designer for every 200 digital designers. As design complexity rises, the limitations of traditional AMS design methods place further demands on AMS designers, who now must account for a widening set of constraints arising not only from design concerns, but also from layout, manufacturing and yield demands.

Because of the traditional limitations in design capabilities, design teams have been largely unable to perform rapid design explorations " virtual "what-if" experiments " to confirm or refute architectural decisions. As a result, design teams have found themselves locked into specific design directions, unknowingly setting the stage for eventual redesigns and costly silicon respins to unravel problems stemming from early decisions.

During design, inefficiencies in traditional verification methods have hampered designers' ability to fine-tune sensitive designs. As product schedules shrink, design teams are forced to limit verification runs, compromising coverage. For highly complex system-level SiPs and SoCs, these limitations are further complicated by technical limitations in their ability to verify analog or RF circuits in the context of the full system.

As designs move to layout, the increased impact of parasitics results in connectivity or design rule check (DRC) errors, requiring further delays to rework layouts. Limitations in modeling accuracy can combine to seriously degrade eventual silicon performance, manufacturing yield, or both. To address these issues, more sophisticated methods draw on detailed representations of circuits based on analysis of the complete three-dimensional electrical environment seen by those circuits. In contrast, simple wire-load models were previously used to predict the performance of critical nets (Figure 2).

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Figure 2: Wire-load models are no longer sufficient to predict net performance; three-dimensional analysis is needed to model the electrical environment.

Assisted Automation
Even as AMS design complexity continues to grow, however, semiconductor companies face one incontrovertible fact: AMS design inherently requires continual manual guidance and careful tuning. By its nature, AMS design depends on the knowledge, experience and talent of engineers to transform design specifications into high-yield, high-performance silicon. As such, this type of design can never be fully automated.

By providing capabilities able to enhance the productivity of analog/mixed-signal design teams, assisted-automation design strategies are beginning to emphasize a more efficient use of limited engineering resources. An important focus for this approach centers on helping designers to cope with the myriad tasks needed to convey the intent of critical design decisions to downstream peers in the silicon design chain.

For example, designers have for years needed to manually define constraints to reflect their design intent in creating specific structures, such as matched circuits for differential amplifiers, Typically, they note such critical constraints as free-text notes within the schematic itself. In turn, the layout engineer would need to methodically comb through a schematic, looking for notes describing such constraints.

With this manual approach, however, success in implementing constraints depends heavily on face-to-face discussions in design review meetings to confirm that layout met all critical constraints. Indeed, this manual approach to constraint definition and implementation increases the likelihood of errors, particularly as design complexity rises.

Constraint-driven design
At the core of emerging assisted-automation strategies, the ability for design teams to maintain design intent throughout the entire design flow is vital in reducing errors introduced through traditional manual methods. Instead of relegating critical design information to informal notes, constraint-driven design methods automate the communication and application of complex design constraints from specifications through layout to verification.

By incorporating constraints in a schematic, for example, designers ensure that their design intent remains a factor in decisions made during downstream phases such as layout. In turn, IC teams can incorporate manufacturing constraints at the earliest stages of design, ensuring that design decisions are made with full knowledge of downstream manufacturability concerns. As a result, engineers at each stage of development can focus their creativity on enhancing IC performance and yield.

This type of constraint-based approach helps eliminate the traditional labor-intensive, error-prone task of constraint definition, propagation, and communication by completely automating constraint management across design, layout and verification. At each stage of design, a design team member can identify constraints by class or specific parameter, and allow those constraints to guide his or her own engineering task, or can override the constraint to meet some higher objective.

In turn, the same team member can add further constraints for propagation to the next stage of development. For example, a designer can embed specific constraints in a schematic needed to meet design objectives for matched circuits, Figure 3, and these constraints will be there for designers downstream and also be accounted for automatically during simulation and layout.

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Figure 3: Assisted automation tools let designs embed design notes for other users, and also take these into account during simulation and layout.

Constraints can drive specific engineering steps such as preliminary placement and routing or simply inform the final decisions made by engineering specialists such as layout engineers. Constraint-driven design, verification and layout help eliminate manual rework while allowing geographically dispersed design teams to rapidly collaborate on delivering verified design intent in optimized silicon.

As a result, this approach can help facilitate rapid parasitic closure and address the broad range of electrical and physical design concerns simultaneously to meet both performance and yield requirements. With the introduction of this constraint-driven methodology, the connection between the design and implementation is complete, allowing for a smoother and less error-prone handoff between increasingly complex stages of IC development. For semiconductor companies, these capabilities translate into faster design time, reduced errors and increased predictability and opportunity for first-pass silicon success.

Critical Standards
Because each individual stage in the IC design chain now impacts overall silicon performance and yield, the ability to easily share knowledge about design and manufacturing, in addition to data, is critical. The need for open interoperability of tools and data has driven growing acceptance of standards such as the OpenAccess standard to provide the kind of open infrastructure needed to integrate design tools and flows. Rather than forcing engineers to maintain a growing set of tool-to-tool data translation scripts, and deal with various formats such as LEF, DEF, and EDIF among others, the use of standard databases provides uniform methods for storing and accessing semiconductor-design data.

Consequently, design teams can utilize more sophisticated design flows able to draw on the new and emerging tools needed to address emerging AMS design challenges. Besides reducing design-support costs, this approach is essential for enabling effective multi-company design chains. Because each tool in each environment works with a common data model and uniform access methods, tools can share data more effectively.

Newer design strategies will leverage assisted automation methods such as constraint-driven design and key standards such as OpenAccess to address emerging AMS IC challenges. As analog content continues to rise in market-leading ICs, this assisted-automation strategy promises to deliver the combination of efficiency, productivity and innovative design capabilities needed to deliver differentiated, high-quality custom silicon on time

About the Authors
Dr. Anthony J. Gadient has over twenty-five years of experience developing and marketing EDA software. He is currently leading the Product Marketing team for Cadence's Virtuoso custom design platform. Prior to joining Cadence, Dr. Gadient helped to found Neolinear and led the development of Neolinear's NeoCell and NeoCircuit products as vice president of Engineering and vice president of Strategic Development. Prior to starting Neolinear, he was the Director of Research at SCRA where he led SCRA's many efforts in the electronics area. Dr. Gadient served as an Officer in the United States Air Force (USAF), where he helped develop the VHDL language. He has published many technical articles and has received numerous awards. Dr. Gadient received his PhD degree from Carnegie Mellon University, MBA from Wright-State University, and BSEE from the University of Virginia.

Steven Lewis is currently a product marketing director for the Virtuoso custom design platform at Cadence Design Systems. He holds over 17 years of EDA experience, and has held a variety of technical, managerial and marketing positions in his fifteen years at Cadence. Prior to Cadence, Mr. Lewis worked at Daisy Systems, Inc. He holds a BSEE from Santa Clara University.